Semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorsMasako Ohta, Tsuneaki Fuse
Life of this patent
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Abstract
A semiconductor device includes a substrate having an active layer, an element region provided in the active layer, a P-type semiconductor region provided in the element region, and first and second N-type semiconductor regions provided in the element region, located on the sides of the P-type semiconductor region, respectively and spaced in a first direction. The device has an N-type MOS transistor and first and second P-type MOS transistors. The N-type MOS transistor has a first gate electrode provided on the P-type semiconductor region. The first P-type MOS transistor has a second gate electrode provided on the first N-type semiconductor region. The second P-type MOS transistor has a third gate electrode provided on the second N-type semiconductor region.
Claims21
A semiconductor device comprising:
- a substrate having an insulating layer and an active layer provided on the insulating layer;
- a first element region provided in the active layer;
- an element-isolating region provided in the active layer, surrounding the first element region and reaching the insulating layer;
- a P-type semiconductor region provided in the first element region and reaching the insulating layer;
- first and second N-type semiconductor regions provided in end parts of the P-type semiconductor region, respectively, spaced apart in a first direction, provided in the first element region, and reaching the insulating layer;
- at least one N-type MOS transistor provided in the P-type semiconductor region and having a first gate electrode provided on the P-type semiconductor region, a direction of a channel length of the N-type MOS transistor substantially corresponding to the first direction;
- at least one first P-type MOS transistor provided in the first N-type semiconductor region and having a second gate electrode provided on the first N-type semiconductor region, a direction of a channel length of the first P-type MOS transistor substantially corresponding to the first direction;
- and
- at least one second P-type MOS transistor provided in the second N-type semiconductor region and having a third gate electrode provided on the second N-type semiconductor region, a direction of a channel length of the second P-type MOS transistor substantially corresponding to the first direction.
A semiconductor device comprising:
- a substrate having an insulating layer and an active layer provided on the insulating layer;
- an element region provided in the active layer;
- an element-isolating provided in the active layer, surrounding the element region and reaching the insulating layer;
- a P-type semiconductor region provided in the element region and reaching the insulating layer;
- an N-type semiconductor region provided in the element region, surrounding the P-type semiconductor region, and reaching the insulating layer;
- an N-type MOS transistor provided in the P-type semiconductor region and having a first gate electrode provided on the P-type semiconductor region;
- and
- a P-type MOS transistor provided in the N-type semiconductor region and having a second gate electrode provided on the N-type semiconductor region.
A semiconductor device comprising:
- a substrate having an insulating layer and an active layer provided on the insulating layer;
- an element region provided in the active layer and having a space in a center part;
- an element-isolating region provided in the active layer and the space of the element region, surrounding the element region and reaching the insulting layer;
- and
- a plurality of gate electrodes provided on the element region and extending in radial directions from the center part of the element region.
Dependencies are inferred from the claim text.