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US 2005/0174168 A1Published application
Differential preamplifier having balanced resistor network
AssigneeTexas Instruments Incorporated
InventorsYukihisa Hirotsugu, Naoyuki Hanajima, Hisao Ogiwara
Life of this patent
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Abstract
The present invention comprises a pair of circuits (171, 172) within the first stage (100) of an AC signal pre-amplifier. The present invention reduces the current mismatch at the base of the first stage transistors (141, 142, 143, 144) resulting in faster switching times by reducing input stage offset and, hence improving input dynamic range.
Claims20
The first stage of a preamplifier circuit, comprising:
- a first differential pair of transistors and a second differential pair of transistors;
- the bases of the first differential pair of amplifying transistors being capacitively coupled to the first side of an input through a first capacitor;
- the bases of the second differential pair of amplifying transistors being capacitively coupled to the second side of an input through a second capacitor;
- a first current loop and a second current loop;
- the first current loop comprised of a first resistor, a first transistor switch and a second resistor;
- the first resistor and second resistor having the same value;
- the second current loop comprised of a third resistor, a second transistor switch and a fourth resistor;
- the third resistor and fourth resistor having the same value;
- the first current loop being coupled to the bases of a first differential pair of amplifying transistors;
- the second current loop being coupled to the bases of a second differential pair of amplifying transistors;
- a third transistor switch being coupled across the bases of the first differential pair of amplifying transistors;
- a fourth transistor switch being coupled across the bases of the second differential pair of amplifying transistors;
- and
- the first current loop and second current loop operable to equalize the charges upon the first transistor and second transistor.
11 more elements
An input preamplifier circuit stage, comprising:
- a first circuit comprised of at least a first pair of differential transistors having an input and providing an output from the first stage of the preamplifier;
- the first pair of differential transistors comprising a first amplifying transistor and a second amplifying transistor;
- a second circuit comprised of at least a second pair of differential transistors having an input, being coupled to the first circuit, and providing an output from the first stage of the preamplifier;
- the second pair of differential transistors comprising a third amplifying transistor and a fourth amplifying transistor;
- the first circuit being coupled to the second circuit through the coupling of the collector of third amplifying transistor to the collector of the first amplifying transistor and the coupling of the collector of fourth amplifying transistor to the collector of the second amplifying transistor;
- a first current loop within the first circuit;
- a second current loop within the second circuit;
- the first current loop comprising a first resistor with a first terminal and second terminal, a first transistor switch with an input and output and a second resistor with a first terminal and second terminal;
- the first resistor and second resistor comprising a pair of balanced resistors;
- the second terminal of the first resistor being coupled to the input of the first transistor switch;
- the second terminal of the second resistor being coupled to the output of the first transistor switch;
- the first terminal of the first resistor and the first terminal of the second resistor being coupled across the bases of the first pair of differential transistors;
- a second transistor switch being coupled across the bases of the first amplifying transistor and the second amplifying transistor;
- the second current loop within the second circuit comprising a third resistor with a first terminal and second terminal;
- a third transistor switch with an input and output;
- a fourth resistor with a first terminal and second terminal, the third and fourth resistors also comprising a pair of balanced resistors;
- the second terminal of the third resistor being coupled to the input of the third transistor switch;
- the second terminal of the fourth resistor being coupled to the output of the third transistor switch;
- the first terminal of the third resistor and the first terminal of the fourth resistor being coupled across the bases of the second differential pair of transistors;
- and
- a fourth transistor switch being coupled across the bases of the third amplifying transistor and the fourth amplifying transistor.
18 more elements
A method of reducing the offset current from a base current compensation circuit, comprising:
- placing a current loop comprised of a balanced pair of resistors opposite each other and a pair of transistor switches opposite each other across the bases of a differential pair of transistors;
- and
- capacitively coupling said current loop to the input of a circuit so that the current loop charges input capacitors so as to decrease the recovery time of the circuit.
Dependencies are inferred from the claim text.