# US 2005/0160383 A1 · Combined e-beam and optical exposure semiconductor lithography

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- Number: US 2005/0160383 A1
- Document ID: US20050160383A1
- Status: Published application
- Kind: A1
- Application number: 11/080,316
- Filed: 2005-03-14
- Published: 2005-07-21
- Earliest claimed: 2002-05-08
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chin-Hsiang Lin
- Web page: https://patentgrep.com/patent/US20050160383A1

## CPC

- G03F 7/2022: {Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 40/00: Manufacture or treatment of nanostructures
- G03F 7/7045: {Hybrid exposures, i.e. multiple exposures of the same area using different types of exposure apparatus, e.g. combining projection, proximity, direct write, interferometric, UV, x-ray or particle beam}
- H01J 37/3174: {Particle-beam lithography, e.g. electron beam lithography}
- H10P 76/2041: {Photolithographic processes}
- H10P 76/2045: {Electron beam lithography processes}
- H01J 2237/31757: hybrid, i.e. charged particles and light, X-rays, plasma
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Combined e-beam and optical exposure lithography for semiconductor fabrication is disclosed. E-beam direct writing to is employed to create critical dimension (CD) areas of a semiconductor design on a semiconductor wafer. Optical exposure lithography is employed to create non-CD areas of the semiconductor design on the semiconductor CD's of the semiconductor design can also be separated from non-CD's of the semiconductor design prior to employing e-beam direct writing and optical exposure lithography.

## Claims

### Claim at position 1

1-12. (canceled)

### Claim 13

A method for separating critical dimensions (CD) of a semiconductor design from a non-CD of the semiconductor design comprising:
applying a CD rule governing which of a plurality of dimensions of the semiconductor design are the CD to each of the plurality of dimensions of the semiconductor design to initially define the CD to a first layer for electron (e-) beam direct writing on a semiconductor wafer; and
defining the non-CD to a second layer for optical exposure lithography on the semiconductor wafer.

### Claim 14 (depends on 13)

The method of claim 13, further initially comprising determining the CD rule.

### Claim 15 (depends on 14)

The method of claim 14, wherein determining the CD rule comprises determining the CD rule as a dimension less than a threshold being a CD.

### Claim 16 (depends on 14)

The method of claim 14, wherein determining the CD rule comprises determining the CD rule as dimensions having a pitch less than a threshold being CD.

### Claim 17 (depends on 13)

The method of claim 13, further comprising, after applying the CD rule to initially define the CD, also defining those of the plurality of dimensions of the semiconductor design as the CD that includes space less than a critical line width between two polygons.

### Claim 18 (depends on 13)

The method of claim 13, further comprising, after applying the CD rule to initially define the CD, adding an extension at one or more of the CD's of the semiconductor design for overlay budgeting.

### Claim 19

A method for separating critical dimensions (CD) of a semiconductor design from a non-CD of the semiconductor design comprising:
defining the CD of the semiconductor design to a first layer for electron (e-) beam direct writing on a semiconductor wafer as gate-shrink polysilicon areas of polysilicon gate layers of the semiconductor design, the semiconductor design also having OD-active layers; and
defining the non-CD of the semiconductor design to a second layer for optical exposure lithography on the semiconductor wafer as non-gate shrink polysilicon areas of the polysilicon gate layers of the semiconductor design.

### Claim 20 (depends on 19)

The method of claim 19, further comprising adding an extension at one or more of the CD of the semiconductor design for overlay budgeting.