Method and apparatus for forming a semiconductor substrate with a layer structure of activated dopants

A transistor for an integrated circuit device, comprising:

• a gate insulating layer formed on a semiconductor substrate;
• a gate conductor formed on the gate insulator layer;
• a first transistor electrode and a second transistor electrode;
• a first and second transistor electrode extension having a first dopant connected, respectively, to each of the first transistor electrode and the second transistor electrode, wherein the first and second transistor electrode extensions abut the gate insulating layer;
• and
• a first and second boundary region having a second dopant configured, respectively, at least partially surrounding each transistor electrode extension, wherein each boundary region has a concentration abruptness of at least 1 nm/decade.

A method of forming a transistor comprising:

• forming a first amorphous region and a second amorphous region in a semiconductor substrate;
• implanting a first dopant in the amorphous regions;
• activating the first dopant in portions of the amorphous regions to form a first boundary region lining the first amorphous region and a second boundary region lining the second amorphous region;
• implanting a second dopant in the amorphous regions;
• and
• activating the second dopant in each amorphous region to form a source extension at least partially surrounded by the first boundary region and a drain extension at least partially surrounded by the second boundary region.