Methods and apparatus for packaging integrated circuit devices

An integrally packaged optronic integrated circuit device comprising:

• an integrated circuit die comprising:
• a crystalline substrate having first and second generally planar surfaces and edge surfaces;
• and
• optronic semiconductor circuitry formed over said first generally planar surface;
• at least one chip scale packaging layer formed over said semiconductor circuitry and said first generally planar surface;
• and
• at least one electrical conductor overlying at least one of said edge surfaces, said at least one electrical conductor being connected to said circuitry by at least one pad formed directly on said first generally planar surface.

A method of producing integrally packaged optronic integrated circuit devices comprising:

• providing a plurality of integrated circuit dies formed on a wafer having first and second generally planar surfaces and optronic semiconductor circuitry formed over said first generally planar surface;
• forming at least one chip scale packaging layer over said semiconductor circuitry and said first generally planar surface;
• separating said integrated circuit dies from each other along dice lines defined in said second generally planar surface, so as to define edge surfaces of said dies while said dies remain attached to said packaging layer;
• forming at least one electrical conductor overlying said second generally planar surface, said at least one electrical conductor being connected to said circuitry by at least one pad formed directly on said first generally planar surface;
• and
• subsequently dicing said wafer to define a plurality of packaged optronic integrated circuit devices.

A method of producing integrally packaged optronic integrated circuit devices comprising:

• providing a plurality of integrated circuit dies formed on a wafer having first and second generally planar surfaces and optronic semiconductor circuitry formed over said first generally planar surface;
• forming at least one chip scale packaging layer over said semiconductor circuitry and said first generally planar surface;
• separating said integrated circuit dies from each other along dice lines defined in said second generally planar surface, so as to define edge surfaces of said dies while said dies remain attached to said packaging layer;
• forming at least one electrical conductor overlying at least one of said edge surfaces, said at least one electrical conductor being connected to said circuitry by at least one pad formed directly on said first generally planar surface;
• and
• subsequently dicing said wafer to define a plurality of packaged optronic integrated circuit devices.