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US 2005/0102340 A1Published application
Apparatus for spreading, scrambling and correlation in a reconfigurable digital signal processor
AssigneeMorpho Technologies
InventorEliseu Chaves Filho
Life of this patent
Estimating the term…
Abstract
A hardware unit within a DSP includes various circuits and components that allow spreading, complex scrambling, and complex correlation to be performed at the software level in a programmable processor at the speed levels required by third generation wireless communication systems.
Claims21
A hardware unit within a digital signal processor (DSP), comprising:
- four polarity circuits, each configured to receive an input value and calculate a negative of the input value;
- four sets of multiplexers, each set comprising two multiplexers, wherein each of the multiplexers in each set receives a corresponding input signal and a corresponding output signal from one of the four polarity circuits;
- a code register coupled to each of the multiplexers, wherein code bits within the code register determine which input the multiplexers select;
- four first arithmetic circuits selectively coupled to receive signals from the multiplexers;
- two second arithmetic circuits selectively coupled to receive signals from the multiplexers;
- and
- two second multiplexers, each configured to receive an output signal from one of the second arithmetic circuits and an output signal from the first arithmetic circuits.
4 more elements
A hardware unit within a CDMA unit within a digital signal processor (DSP), the hardware unit y comprising:
- means for calculating the negative of an input signal;
- 2-to-1 multiplexers coupled to the means for calculating, wherein each of the multiplexers selects either the input signal or the negative of the input signal;
- a code register coupled to each of the multiplexers, wherein code bits within the code register determine which input the multiplexers select;
- first arithmetic circuits coupled to the output of the multiplexers to add or subtract inputs to the arithmetic circuits;
- second arithmetic circuits coupled to at least the 2-to-1 multiplexers;
- and
- two multi-bit 2-to-1 multiplexers coupled to the second arithmetic circuits, wherein the multi-bit 2-to-1 multiplexers select signals for use by the DSP.
4 more elements
Dependencies are inferred from the claim text.