Method and system for producing a reduced bounding box
OwnerRobert Sewardinventor
Life of this patent
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Abstract
Systems, methodologies, media, and other embodiments associated with reducing a bounding box for a net in a VLSI design of cells, where a cell may have two or more pins by which it can be connected to one or more other cells in the design, is described. One exemplary method may include receiving the design, producing an initial bounding box for a net in the design, and reducing the initial bounding box to a reduced bounding box.
Claims29
A method for producing a reduced bounding box for a net in a VLSI design of cells, where at least one cell in the design includes two or more pins by which the cell can be connected to at least one other cell in the design, the method comprising:
- creating a set of electronic records configured to store information about one or more pins and one or more ports connected to the net in the design;
- storing data about the one or more pins in one or more data structures configured to store pin data, where the data about the one or more pins facilitates relating the one or more pins to one or more electronic records in the set of electronic records;
- selectively arranging the set of electronic records in a pre-determined order;
- producing an initial bounding box for the net in the design;
- analyzing the selectively arranged set of electronic records to identify a corner case of pins in the initial bounding box;
- selectively removing pins in a corner case of pins to produce an intermediate bounding box from the initial bounding box;
- reducing the size of the intermediate bounding box by repetitively selectively removing one or more pins from inclusion in the intermediate bounding box;
- and
- producing the reduced bounding box by further reducing the size of the intermediate bounding box by repetitively selectively moving an edge of the intermediate bounding box.
A computer-readable medium storing processor executable instructions operable to perform a method for producing a reduced bounding box for a net in a VLSI design of cells, where at least one cell in the design includes two or more pins by which the cell can be connected to at least one other cell in the design, the method comprising:
- creating a set of electronic records configured to store information about one or more pins and one or more ports connected to the net in a design for which the reduced bounding box is to be produced;
- storing data about the one or more pins in one or more data structures configured to store pin data, where the data about the one or more pins facilitates relating the one or more pins to one or more electronic records in the set of electronic records;
- selectively arranging the set of electronic records in a pre-determined order;
- producing an initial bounding box for the net in the design;
- analyzing the selectively arranged set of electronic records to identify a corner case of pins in the initial bounding box;
- selectively removing pins in a corner case of pins to produce an intermediate bounding box from the initial bounding box;
- reducing the size of the intermediate bounding box by repetitively selectively removing one or more pins from inclusion in the intermediate bounding box;
- and
- producing the reduced bounding box by further reducing the size of the intermediate bounding box by repetitively selectively moving an edge of the intermediate bounding box.
A method for computing a reduced bounding box for a net in a VLSI design of cells, comprising:
- receiving a VLSI design of cells where at least one cell in the VLSI design of cells includes more than one pin by which it can be connected to at least one other cell in the design;
- producing an initial bounding box for the net in the design;
- and
- computing the reduced bounding box by reducing the initial bounding box.
A computer-readable medium storing processor executable instructions operable to perform a method for computing a reduced bounding box for a net in a VLSI design of cells, comprising:
- receiving a VLSI design of cells where at least one cell in the VLSI design of cells includes more than one pin by which it can be connected to at least one other cell in the design;
- producing an initial bounding box for the net in the design;
- and
- computing the reduced bounding box by reducing the initial bounding box.
A system, comprising:
- a bounding box memory configured to store design data associated with a net in a design for which a bounding box is to be reduced, where at least one cell in the design includes two or more pins by which it can be connected to at least one other cell in the design;
- and
- a reducing logic operably connected to the bounding box memory, where the reducing logic is configured to compute a reduced bounding box.
A system for producing a minimal bounding box for a net in a VLSI design of cells, where one or more cells may include two or more pins by which the one or more cells can be connected to one or more other cells, the system comprising:
- means for receiving a VLSI design of cells;
- means for producing an initial bounding box;
- means for identifying pins in corners that may be excluded;
- and
- means for moving edges in the bounding box.
Dependencies are inferred from the claim text.