Systems and methods for identifying erroneous transactions
AssigneeHewlett-Packard Development Company, L.P.
InventorsZachary Smith, John Maly, Ryan Thompson
Life of this patent
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Abstract
Disclosed are systems and methods for identifying erroneous transactions. In one embodiment, a system and a method pertain to monitoring an interface, determining information related to termination of a test case, and after the test case has terminated, identifying an incomplete transaction that should have completed prior to termination of the test case.
Claims29
A method for identifying erroneous transactions that occur during processor architecture verification testing, the method comprising:
- monitoring an interface;
- determining information related to termination of a test case;
- and
- after the test case has terminated, identifying an incomplete transaction that should have completed prior to termination of the test case.
A system for identifying erroneous transactions, the system comprising:
- means for monitoring all ports of an interface;
- means for determining information related to termination of a test case;
- and
- means for identifying an incomplete transaction that should have completed prior to termination of the test case.
A virtual bus interface (VBI) stored on a computer-readable medium, the VBI comprising:
- logic configured to monitor a point-to-point (P2P) interface;
- logic configured to determine a time at which a break signal was asserted;
- logic configured to identify transactions that are pending after the break signal was asserted;
- and
- logic configured to determine which of the pending transactions are erroneous.
A processor architecture verification system, comprising:
- a register transfer language (RTL) simulator that simulates operation of a processor and generates a first output in a first format, the RTL simulator including an interface;
- a golden simulator that simulates operation of the processor and generates a second output in a second format;
- a translator that translates at least one of the outputs for comparison with the other output, the translator including a virtual bus interface (VBI) that comprises logic configured to monitor a point-to-point (P2P) interface, logic configured to determine a time at which a break signal was asserted, logic configured to identify transactions that are pending after a break command was issued, and logic configured to determine which of the pending transactions are erroneous;
- and
- a comparator that compares the first and second outputs after translation of the at least one output.
Dependencies are inferred from the claim text.