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US 2005/0097291 A1Published application
Multiple data rate bus using return clock
AssigneeInfineon Technologies North America Corp.
InventorJonghee Han
Life of this patent
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Abstract
A method and apparatus for ensuring safe transmission of data on a bus line. In one embodiment, within a given clock period, first data is driven on a data bus and a strobe signal is transmitted, via a first signal path, to a receiving circuit indicating the validity of the first data on the data bus. A return signal received within the given clock period indicates an assumed arrival of the strobe signal at the receiving circuit. In response to receiving the return signal, second data is driven onto the data bus.
Claims42
A method of operating a control circuit in a multiple data rate memory device, comprising, within a given clock period:
- driving first data on a data bus;
- transmitting, via a first signal path, a strobe signal to a receiving circuit indicating the validity of the first data on the data bus;
- receiving a return signal indicating an assumed arrival of the strobe signal at the receiving circuit;
- and
- in response to receiving the return signal, driving second data on the data bus.
2 more elements
A method of operating a multiple date rate memory device, comprising, within a given clock period:
- (a) driving a first data on a data bus;
- (b) issuing a strobe signal from a controller;
- (c) receiving, by a receiving circuit, the strobe signal a period of time after issuing the strobe signal;
- (d) in response to receiving the strobe signal by the receiving circuit, latching in the first data from the data bus;
- (e) receiving, by the controller, the strobe signal a period of time after issuing the strobe signal;
- and
- (f) in response to receiving the strobe signal by the controller, driving a second data on a data bus.
4 more elements
A method of operating a multiple date rate memory device, comprising, within a given clock period:
- (1) by a driver controller:
- driving first data on a data bus;
- transmitting a data strobe signal to a receiver via a forward signal path;
- receiving the data strobe signal via a return signal path;
- and
- in response to receiving the strobe signal, driving second data on the data bus;
- and
- (2) by a receiver:
- receiving the strobe signal via the forward signal path;
- and
- in response to receiving the strobe signal, latching the first data in from the data bus.
8 more elements
A method of operating a control circuit in a multiple date rate memory device, comprising, within a given clock period:
- enabling a driver to drive a first data on a data bus;
- issuing a strobe signal to a receiving circuit via a forward signal path to indicate the presence of the first data on the data bus;
- receiving the strobe signal via a return signal path, wherein receipt of the strobe signal indicates an assumed arrival of the strobe signal at the receiving circuit via the forward signal path;
- and
- in response to receiving the strobe signal, enabling a driver to drive a second data on the data bus.
2 more elements
A multiple data rate memory device, comprising:
- a controller configured to generate one or more driver-enable signals and a strobing clock signal;
- a data bus;
- a driver circuit configured to drive a first data and a second data on the data bus in response to the one or more driver-enable signals from the controller;
- a receiver circuit configured to receive the first and second data via the data bus, the receiver circuit configured to latch the first and second data in response to the strobing clock signal generated by the controller;
- a strobe clock signal line to propagate the strobing clock signal from the controller to the receiver circuit;
- and
- a round-trip path comprising a return path for the strobing clock signal back to the controller;
- wherein the controller is configured to enable the driver circuit to drive the first data on the data bus, generate the strobing clock signal propagated to the receiver circuit on the strobe clock signal line, receive the strobing clock signal on the round-trip path and, in response to receiving the strobe clock signal, enable the driver circuit to drive the second data on the data bus.
5 more elements
A multiple data rate memory device, comprising:
- a driver configured to drive at least a first data and a second data;
- a receiver coupled to the driver;
- a controller coupled to the driver and configured to enable the driver to drive the first data and the second data;
- a strobe clock signal line coupled between the receiver and controller and configured to propagate a strobe clock signal;
- and
- a return clock signal line coupled at an output end to the controller and configured to propagate a return clock signal signaling the controller to enable the driver to drive the second;
- wherein the return clock signal is timed off of the strobe clock signal.
4 more elements
A clocking circuit in a multiple data rate memory device, comprising:
- a controller comprising a strobe clock signal output and a return clock signal input and configured to issue a first enable signal and a second enable signal, the first enable signal enabling a plurality of drivers to drive respective first data on respective data lines, and the second enable signal enabling the plurality of drivers to drive respective second data on their respective data lines;
- a strobe clock signal line coupled to the strobe clock signal output;
- and
- a return clock signal line coupled to the return clock signal input;
- wherein the strobe clock signal line defines an initial portion of a round-trip path and the return clock signal line defines a terminal portion of the round-trip path;
- and wherein the controller is configured to:
- respond to an external clock signal by pulling a strobe clock signal to a first state on the strobe clock signal line and pulling the first enable signal to an active state;
- receive a return clock signal on the return clock signal line a period of time after pulling the strobe clock signal to the first state, wherein the return clock signal is timed off of the strobe clock signal and indicates an assumed receipt of the strobe clock signal in the active state by receiving circuitry coupled to the respective data lines and configured to latch in the first and second data from the data lines in response to the strobe clock signal;
- and
- respond to the received return clock signal by pulling the second enable signal to an active state.
7 more elements
A multiple data rate memory device, comprising:
- a bidirectional data bus;
- a first driver circuit coupled to the bus and configured to propagate a first data and a second data in a first direction along the bus;
- a first receiver circuit coupled to an end of the bus opposite the first driver circuit and configured to latch the first and second data in response to a first strobe clock signal;
- a second driver circuit coupled to the bus and configured to propagate a third data and a fourth data in a second direction along the bus;
- a second receiver circuit coupled to an end of the bus opposite the second driver circuit and configured to latch the third and fourth data in response to a second strobe clock signal;
- a first controller configured to enable the first driver circuit and to generate the first strobe clock signal;
- a second controller configured to enable the second driver circuit and to generate the second strobe clock signal;
- a first strobe clock signal line to propagate the first strobe clock signal from the first controller to the first receiver circuit;
- a first round-trip path comprising a first return path for the first strobe clock signal back to the first controller;
- a second strobe clock signal line to propagate the second strobe clock signal from the second controller to the second receiver circuit;
- and
- a second round-trip path comprising a second return path for the second strobe clock signal back to the second controller.
9 more elements
Dependencies are inferred from the claim text.