I2C device including bus switches and programmable address

A method for utilizing a device coupled to a serial communications bus, comprising:

• said device including a main section, address logic, switches, and switch logic;
• coupling said device to said communications bus utilizing said switches;
• controlling a current position of said switches utilizing said switch logic;
• controlling whether said main section, said address logic, said switch logic, or a combination of said main section, address logic, and switch logic is currently coupled to said communications bus utilizing said switch logic.

An I2C device coupled to an I2C serial communications bus having only a clock signal line and a data signal line, said I2C device comprising:

• a main section;
• address logic;
• switches connected to said communications bus;
• switch logic for controlling a current position of said switches coupled to said switch logic;
• said switches controlling whether said main section, said address logic, said switch logic, or a combination of said main section, address logic, and switch logic is currently coupled to said communications bus;
• said main section, said address logic, and said switch logic being logically removed from said communications bus when said switches are in a first position;
• said main section being logically removed from said communications bus when said switches are in a second position;
• said address logic and said switch logic remaining logically connected to said communications bus when said switches are in a second position;
• said main section, said address logic, and said switch logic being logically connected to said communications bus when said switches are in a third position;
• said switches including an input switch device and an output switch device;
• said input switch device being a double pole rotary switch having a first pole coupled to said data signal line and a second pole coupled to said clock signal line;
• said output switch device being a double pole rotary switch having a first pole coupled to said data signal line and a second pole coupled to said clock signal line;
• at least one second device coupled to said communications bus after said device;
• said main section, said address logic, and said switch logic being logically connected to said communications bus when said output switch device is in a fourth position;
• said at least one second device being logically removed from said communication bus when said output switch device is in said fourth position;
• said main section, said address logic, and said switch logic being logically removed from said communications bus when said input switch device is in a fourth position;
• said at least one second device being logically removed from said communication bus when said input switch device is in said fourth position;
• said address logic for storing an address for said device, said device being addressed on said communications bus utilizing said address;
• said device having a hardwired address;
• and
• said address stored in said address logic overriding at least a portion of said hardwired address.