Memory systems and methods
AssigneeHewlett-Packard Development Company, L.P.
InventorsWilliam Oberlin, Mark Simpson, Srinivas Venkataraman
Life of this patent
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Abstract
Memory systems and methods are described. In one embodiment, a circuit board has front and back surfaces. At least one memory device having a plurality of pins is mounted on the front surface of the circuit board. At least one other memory device having a plurality of pins is mounted on the back surface of the circuit board. The memory devices are mounted on the circuit board such that at least some pins from the one memory device align with at least some pins of the other memory device to provide aligned pin pairs. A via is disposed in the circuit board and extends between and connects individual pins of an aligned pin pair.
Claims29
An apparatus comprising:
- a circuit board having front and back surfaces;
- at least one memory device having a plurality of pins mounted on the front surface of the circuit board;
- at least one other memory device having a plurality of pins mounted on the back surface of the circuit board;
- said memory devices being mounted on the circuit board such that at least some pins from the one memory device align with at least some pins of the other memory device to provide aligned pin pairs;
- and
- a via disposed in the circuit board and extending between and connecting individual pins of an aligned pin pair.
An apparatus comprising:
- a circuit board having front and back surfaces;
- a first plurality of memory devices, each memory device having a plurality of address pins and control pins mounted on the front surface of the circuit board;
- a second plurality of memory devices, each memory device having a plurality of address pins and control pins mounted on the back surface of the circuit board;
- said memory devices being configured in a dual bank configuration;
- said memory devices being mounted on the circuit board such that at least some address and control pins from a front surface mounted memory device share individual respective vias with at least some corresponding address and control pins of a back surface-mounted memory device;
- a memory controller mounted on the circuit board and operably connected with the first and second plurality of memory devices;
- wherein a first group of address pins are interconnected with the memory controller using a first topology and a second group of address pins are interconnected with the memory controller using a second different topology.
An apparatus comprising:
- a circuit board having front and back surfaces;
- at least one memory means mounted on the front surface of the circuit board, said memory means comprising address means and control means;
- at least one other memory means mounted on the back surface of the circuit board, said other memory means comprising address means and control means;
- means extending through the circuit board and operably connecting individual address means and control means from the one memory means with individual address means and control means from the other memory means;
- said means extending through the circuit board being shared between individual respective address means and control means.
A method comprising:
- providing a circuit board having front and back surfaces;
- mounting a first plurality of memory devices on the front surface of the circuit board, each memory device having a plurality of address pins and control pin;
- and
- mounting a second plurality of memory devices on the back surface of the circuit board, each memory device having a plurality of address pins and control pins;
- said acts of mounting being sufficient such that at least some address and control pins from a front surface-mounted memory device share individual respective vias with at least some corresponding address and control pins of a back surface-mounted memory device.
Dependencies are inferred from the claim text.