Method and apparatus for supplementary command bus
AssigneeMicron Technology, Inc.
InventorPaul LaBerge
Life of this patent
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Abstract
An electronic system according to various aspects of the present invention includes a memory having a location-specific command interface and a general command interface. The memory communicates with other components in the system via a main command bus configured to transfer address-specific commands and a supplementary command bus configured to transfer general commands. Commands may be received by the memory simultaneously at the respective interfaces.
Claims18
A DDR memory device having an interface, wherein the interface comprises a general command interface configured to receive a general command.
A SDRAM memory device having an interface, wherein the interface comprises a general command interface configured to receive a general command.
A memory device comprising:
- an interface that is configured to communicate with a supplementary control bus, wherein the supplementary control bus comprises:
- a supplementary command bus, a supplementary chip select bus, and a supplementary bank select bus;
- wherein the supplementary command bus is a one-bit bus that is configured to communicate a supplementary command bit, and
- wherein assertion of the supplementary command bit causes execution of a PRECHARGE command on a first memory bank that is identified by signals from the supplementary chip select bus and the supplementary bank select bus.
A memory comprising:
- an interface that is configured to communicate with a supplementary control bus, wherein the supplementary control bus comprises:
- a supplementary chip select bus, and a supplementary bank select bus;
- wherein activation of the supplementary chip select bus causes execution of a PRECHARGE command on a first memory bank that is identified by signals on the supplementary chip select bus and the supplementary bank select bus.
Dependencies are inferred from the claim text.