CMOS isolation cell for embedded memory in power failure environments
AssigneeLSI Logic Corporation
InventorsBrian Day, Frantisek Gasparik
Life of this patent
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Abstract
An embedded memory on an integrated circuit chip is capable of being isolated from other on chip and off chip circuitry during power failure modes on the integrated circuit chip. The embedded memory preferably has its own external power supply. When power on chip fails or falls below a threshold level, input to and output from the embedded memory is prohibited by CMOS isolation cells. The CMOS isolation cells are controlled by enable signals and the power level of other power supplies within the integrated circuit.
Claims38
An integrated circuit, comprising:
- a substrate comprising:
- core logic circuitry;
- isolation cell circuitry;
- and
- an embedded memory coupled to the core logic circuitry,
- wherein the embedded memory is capable of being electrically isolated from the core logic circuitry by the isolation cell circuitry.
An isolation cell for isolating an embedded memory from other circuitry on an integrated circuit, comprising:
- a totem pole arrangement of switches such that each drain and source terminal the switches are connected to one of the group consisting of drain terminals of other switches in the totem pole arrangement, source terminals of other switches in the totem pole arrangement, power, and ground, the totem pole arrangement of switches receiving signal for an embedded memory, the totem pole arrangement of switches providing an output signal to the embedded memory;
- and
- a latch circuit for latching the output signal from the totem pole arrangement of switches, the output signal being supplied to the embedded memory.
A method for isolating an embedded memory on an integrated circuit, comprising:
- Detecting a power level drop below a power threshold level for non-storage circuitry on an integrated circuit;
- and
- Disabling input to and output from an embedded memory on the integrated circuit in response to the power level drop of the core logic circuitry.
An integrated circuit, comprising:
- an embedded memory;
- and
- isolation circuitry for preventing data transfers to and from the embedded memory when a power level on the integrated circuit falls below a predetermined threshold.
An integrated circuit having an embedded memory, comprising:
- embedded means for storing data located on a substrate;
- means for isolating the embedded means for storing data, the isolating means capable of preventing data to be written to the embedded means for storing data when a power fault is detected on the integrated circuit.
Dependencies are inferred from the claim text.