Phase change based memory device and method for operating same
AssigneeSTMicroelectronics S.r.l.
InventorHerman Ma
Life of this patent
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Abstract
A circuit and method are disclosed for a memory device, such as a phase change memory. Specifically, there is disclosed a memory having a plurality of columns of memory cells, with each column of memory cells being coupled to a bit or data line. Each memory cell includes a programmable resistive element coupled in series with a select transistor. Each bit line is coupled to a distinct reference cell and a distinct transistor. The transistor is coupled between the corresponding bit line and a reference voltage, such as ground. During a memory read operation, the transistor, reference cell and addressed memory cell form a differential amplifier circuit. The output of the differential amplifier circuit is coupled to the data output terminals of the phase change memory.
Claims35
A memory device, comprising:
- an array of memory cells arranged in row and columns, each memory cell comprising a select transistor and an electrically programmable resistive element coupled in series therewith, each column of memory cells being coupled to a bit line, each row of memory cells being coupled to a word line, the select transistor in each memory cell having a control terminal coupled to a corresponding word line;
- address circuitry for receiving an address value and driving a word line corresponding thereto to a voltage level to activate select transistors of memory cells coupled to the word line corresponding to the address value;
- a transistor coupled between a first bit line and a first reference voltage level;
- a reference cell coupled to the first bit line, comprising a select transistor and a resistive element coupled in series therewith, the reference cell, the transistor and an addressed memory cell in the column of memory cells coupled to the first bit line forming a differential amplifier circuit;
- and
- control circuitry having an output coupled to a control terminal of the transistor for activating the transistor during a memory read operation.
An electronics device, comprising:
- a memory, comprising:
- an array of memory cells arranged in rows and columns of memory cells, each memory cell comprising a select transistor and a programmable resistive element coupled in series therewith, each column of memory cells being coupled to a single bit line, each row of memory cells being coupled to a single word line, the select transistor in each memory cell having a control terminal coupled to a corresponding word line;
- address circuitry for receiving an address value and driving a word line corresponding thereto to a voltage level to activate select transistors of memory cells coupled to the word line corresponding to the address value;
- a transistor coupled between at least one bit line and a reference voltage level;
- a reference cell coupled to the at least one bit line, comprising a select transistor and a resistive element coupled in series therewith;
- a first load component coupled between a second reference voltage level and the memory cells in the column of memory cells coupled to the at least one bit line;
- a second load component coupled between the second reference voltage level and the reference cell, the first and second load components, the reference cell, the transistor and an addressed memory cell in the column of memory cells coupled to the at least one bit line forming a differential amplifier circuit;
- and
- control circuitry having an output coupled to a control terminal of the transistor for activating the transistor during a memory read operation.
A system, comprising:
- a memory, comprising:
- a memory array of memory cells arranged in rows and columns, each column of memory cells connected to a bit line and each row of memory cells connected to a word line;
- a transistor having a first conduction terminal coupled to at least one bit line, a second conduction terminal coupled to a first reference voltage level and a control terminal;
- and
- a reference cell coupled to the at least one bit line, the reference cell, the transistor and an addressed memory cell in the column of memory cells coupled to the at least one bit line forming a differential amplifier circuit having an output signal coupled to a data output terminal of the memory.
An integrated circuit, comprising:
- a plurality of memory cells, each memory cell coupled to a data line;
- a reference cell coupled to the data line;
- a transistor coupled between the data line and a reference voltage;
- and
- a circuit for selecting one memory cell at a time, wherein the selected memory cell, the reference cell, and the transistor form a differential amplifier circuit.
Dependencies are inferred from the claim text.