Electrical sensing apparatus and method utilizing an array of transducer elements
AssigneeHarusaki Technologies, LLC
InventorsJohn Scott-Thomas, Paul Hua, George Chamberlain
Life of this patent
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Abstract
Many electrical sensing devices include an array of transducer elements for converting external stimuli to electrical indications. Novel technologies to realize improvements in low power consumption, low noise, and analog output path which occupies minimal die area while maintaining certain data rates are disclosed. A two stage pipeline architecture of the invention in the analog output path maintains fast pixel rates with minimal ADC (analog digital converter) arrangement. A novel power supply and the use of differential amplifiers in connection with a black signal level as a reference voltage are also described.
Claims25
1-41. (canceled)
47:
- An electrical sensor apparatus comprising:
- an array of transducer elements arranged in a (s×t) matrix where s is the number of rows and t is the number of columns, each transducer element adapted to produce an electrical indication in response to external stimuli incident thereon;
- a plurality t of first stage amplifiers, each first stage amplifier connected to a column of transducer elements;
- a plurality u of data bus lines, each of the data bus lines requiring a substantially similar predetermined duration of time d to settle during a transfer of an electrical indication to the data bus line, wherein:
- t>(n*u),
- where n is a positive integer and every u-th first stage amplifier is connected to the same data bus line;
- a plurality u of second stage amplifiers for generating outputs indicative of the external stimuli, each second stage amplifier being connected to a data bus line;
- wherein the first and second stage amplifiers are in either one of the following configurations, a source follower or a differential amplifier, the first stage amplifiers having associated capacitors for sampling and buffering the amount of charge proportional to the electrical indications of the external stimuli;
- and
- the plurality t of first stage amplifiers being adapted to drive the data bus lines cyclically so that each data bus line is driven at least once, with an interval between two successive bus drives being at least the predetermined duration of time d.
48:
- The electrical sensor apparatus according to claim 47, further comprising a variable current source for supplying two or more current levels to the first stage amplifiers in response to modes of operation of the first stage amplifiers.
49:
- The electrical sensor apparatus according to claim 47, wherein each first stage amplifier comprises a switch for controlling a current source of each column of transducers to prevent leakage of the charge buffered in the associated capacitor.
50:
- The electrical sensor apparatus according to claim 48, wherein the variable current source comprises two branches and a switch for switching between the branches to provide more power while sampling a column or driving a data bus line and a less power during the other mode of operation.
51:
- The electrical sensor apparatus according to claim 50, wherein either one or both of the first and second stage amplifiers include a black level signal as a reference voltage.
52:
- The electrical sensor apparatus according to claim 51, further comprising one or both of the followings, an ADC or PGA, connected to the second stage amplifiers to which the second stage amplifiers provide the output indicative of the external stimuli.
53:
- The electrical sensor apparatus according to claim 49, wherein the switch is connected to the current source and is operable in a predetermined time delayed relationship with the sampling by the first stage amplifiers.
54:
- The electrical sensor apparatus according to claim 53, wherein each first stage amplifier comprises further a dc offset capacitor for storing charge proportional to a dc offset voltage and a switched circuit operable in response to the resetting of transducers so that the amount of charge buffered in the associated capacitor represents either double sampling or correlated double sampling of each transducer.
55:
- The electrical sensor apparatus according to claim 54, wherein either one or both of the first and second stage amplifiers include a black signal level as a reference voltage.
56:
- The electrical sensor apparatus according to claim 55, comprising further one or both of the followings, an ADC or PGA, connected to the second stage amplifiers to which the second stage amplifiers provide the output indicative of the external stimuli.
57:
- The electrical sensor apparatus according to claim 52, wherein the transducer elements are one selected from a group consisting of CMOS optical elements, capacitive sensors, mechanical transducers, acoustic transducers, electromagnetic wave transducers and the external stimulus is one of the following visible or invisible light, including IR and thermal rays, radio waves, X-rays, acoustic waves, mechanical stimuli consisting of any of the following, pressure, mechanical strain, and dislocation.
58:
- The electrical sensor apparatus according to claim 56, wherein the transducer elements are one selected from a group consisting of CMOS optical elements, capacitive sensors, mechanical transducers, acoustic transducers, electromagnetic wave transducers and the external stimulus is one of the following visible or invisible light, including IR and thermal rays, radio waves, X-rays, acoustic waves, mechanical stimuli consisting of any of the following, pressure, mechanical strain, and dislocation.
59:
- A method of generating electrical signals from an array of transducer elements arranged in groups, each element producing an electrical indication in response to an external stimulus incident thereon comprising, steps of:
- sampling the array of transducer elements in a first predetermined sequence according to a double sampling or correlated double sampling technique to read the electrical indications out to a plurality of first stage amplifiers that each include an associated capacitor, a dc offset capacitor and a switching circuit, wherein the sampling includes:
- buffering in the associated capacitor charge proportional to the electrical indication from a group of the transducers;
- storing in the dc offset capacitor a dc offset signal;
- and
- operating, in response to resetting of transducers, the switching circuit for preventing a leakage from the associated capacitor and for ensuring the charge in the associated capacitor to be representative of double sampling or correlated double sampling of a transducer in the group;
- driving in a second predetermined sequence a plurality of data bus lines to transfer data corresponding to the electrical indications from the first stage amplifiers to a plurality of second stage amplifiers such that the data is transferred from every n-th first stage amplifiers, n being a positive integer, each data bus line requiring a predetermined duration of time to settle for each transfer;
- and
- generating the electrical signals indicative of the external stimuli, in that each data bus line is driven at least once for transfer of the data with an interval between successive transfers being at least a predetermined duration of time.
60:
- A method of generating electrical signals from an array of transducer elements arranged in groups, each element producing an electrical indication in response to an external stimulus incident thereon comprising, steps of:
- sampling the array of transducer elements in a first predetermined sequence according to a double sampling or correlated double sampling technique to read the electrical indications out to a plurality of first stage amplifiers that each include an associated capacitor, a dc offset capacitor and a switching circuit, wherein the sampling includes:
- buffering in the associated capacitor charge proportional to the electrical indication from a group of the transducers;
- storing in the dc offset capacitor a dc offset signal;
- and
- operating, in response to resetting of transducers, the switching circuit for preventing a leakage from the associated capacitor and for ensuring the charge in the associated capacitor to be representative of double sampling or correlated double sampling of a transducer in the group;
- driving in a second predetermined sequence a plurality of data bus lines to transfer data corresponding to the electrical indications from the first stage amplifiers to a plurality of second stage amplifiers such that the data is transferred from every individual first stage amplifier one after the other in sequence, each data bus line requiring a predetermined duration of time to settle for each transfer;
- and
- generating the electrical signals indicative of the external stimuli, in that each data bus line is driven at least once for transfer of the data with an interval between successive transfers being at least a predetermined duration of time.
61:
- A method of generating electrical signals from an array of transducer elements arranged in groups, each element producing an electrical indication in response to an external stimulus incident thereon comprising, steps of:
- sampling the array of transducer elements in a first predetermined sequence according to a double sampling or correlated double sampling technique to read the electrical indications out to a plurality of first stage amplifiers that each include an associated capacitor, a dc offset capacitor and a switching circuit, wherein the sampling includes:
- buffering in the associated capacitor charge proportional to the electrical indication from a group of the transducers;
- storing in the dc offset capacitor a dc offset signal;
- and
- operating, in response to resetting of transducers, the switching circuit for preventing a leakage from the associated capacitor and for ensuring the charge in the associated capacitor to be representative of double sampling or correlated double sampling of a transducer in the group;
- driving in a second predetermined sequence a plurality of data bus lines to transfer data corresponding to the electrical indications from the first stage amplifiers to a plurality of second stage amplifiers, each data bus line requiring a predetermined duration of time to settle for each transfer;
- and
- generating the electrical signals indicative of the external stimuli, in that each data bus line is driven at least once for transfer of the data with an interval between successive transfers being at least a predetermined duration of time.
62:
- The method of generating electrical signals from an array of transducer elements according claim 59 comprising a further step of:
- supplying current to the first stage amplifiers at a different level, depending on the mode of operation of the first stage amplifiers.
63:
- The method of generating electrical signals from an array of transducer elements according claim 60 comprising a further step of:
- supplying current to the first stage amplifiers at a different level, depending on the mode of operation of the first stage amplifiers.
64:
- The method of generating electrical signals from an array of transducer elements according claim 61 comprising a further step of:
- supplying current to the first stage amplifiers at a different level, depending on the mode of operation of the first stage amplifiers.
65:
- The method of generating electrical signals from an array of transducer elements according claim 59 wherein the transducer elements in an array are arranged in rows and columns and each group of transducer elements comprises a column.
66:
- The method of generating electrical signals from an array of transducer elements according claim 60 wherein the transducer elements in an array are arranged in rows and columns and each group of transducer elements comprises a column.
67:
- The method of generating electrical signals from an array of transducer elements according claim 61 wherein the transducer elements in an array are arranged in rows and columns and each group of transducer elements comprises a column.
68:
- An electrical sensor apparatus comprising:
- an array of transducer elements arranged in a plurality t of groups where each transducer element is adapted to produce an electrical indication in response to external stimuli incident thereon;
- a plurality t of first stage amplifiers connected to the plurality of groups of transducer elements for receiving the electrical indications from each of the transducer elements;
- a number u of second stage amplifiers for generating outputs indicative of the external stimuli;
- a number u of data bus lines coupled to the number u of second stage amplifiers for transferring the electrical indications from the first stage amplifiers to the second stage amplifiers;
- wherein the data bus lines exhibit a substantially similar time d for an electrical indication to settle and wherein u is determined by the following formula:
- t≧(n*u)
- where n is a positive integer and every u-th first stage amplifier is connected to the same data base line;
- p1 wherein the first and second stage amplifiers are in either one of the following configurations, a source follower or a differential amplifier, the first stage amplifiers having associated capacitors for sampling and buffering the amount of charge proportional to the electrical indications of the external stimuli;
- and
- the plurality t of first stage amplifiers being adapted to drive the data bus lines cyclically so that each data bus line is driven at least once, with an interval between two successive bus drives being at least the predetermined duration of time d.
69:
- The electrical sensor apparatus according to claim 68 wherein the minimum number u of data bus lines is determined by the settling time d in accordance with the formula:
- u≧d/T ,
- where T is a clock period for passing one of the electrical indications from one of the first stage amplifiers to one of the data bus lines;
- and wherein for sub-sampling of every m-th first stage amplifiers, u is determined by the following formula:
- u=p*m+1≧minimum u,
- where p is any positive integer.
70:
- The electrical sensor apparatus according to claim 68 wherein the data bus lines are substantially of equal length.