Method for an image reducing processing circuit

A method for an image reducing processing circuit including the memory architecture of two First-In-First-Out (FIFO) units for simplifying the using of access frequency and memory depth, said method comprising the following steps of

• (1) providing an input processing receiving input image data and delivering said image data;
• (2) providing a horizontal direction image processing receiving said image data from said step (1), quantifying said image data in said horizontal direction, and then transferring said image data to column signals with a row column type;
• (3) providing a first step First-In-First-Out (FIFO) receiving said image data from said step (2) to read and write said image data with said first access frequency, and having a plurality of First-In-First-Out (FIFO) sub unit receiving and delivering said image data in sequence;
• (4) providing a vertical direction image processing receiving said image data from said step (3), reading and writing completely said image data, quantifying said image data in said vertical direction, and then transferring said image data to row signals with a row column type;
• (5) providing a second step First-In-First-Out (FIFO) receiving said image data from said step (4), and having a First-In-First-Out (FIFO) memory element implementing said readout and writing of said image data on said first access frequency and a second access frequency;
• and
• (6) providing an output processing working on the second access frequency, receiving said image data from said setp (5), and outputting reduced image data.