[clock signal amplifying method and driving stage for lcd driving circuit ]
AssigneeAu Optronics Corporation
InventorsJian-Shen Yu, Shih-Chian Liu
Life of this patent
Estimating the term…
Abstract
A clock signal amplifying method and driving stage for LCD driving circuit is provided. The driving stage includes a clock input, a level shifter, and an output buffer. Firstly, the clock input receives a cock signal oscillating between a high original level and a low original level. Thereafter, a level shifter is biased at a high target level and a low target level, and amplifies the clock signal to a relay signal, which oscillates between a high relay level and a low relay level. Lastly, the output buffer is biased at the high relay level and the low relay level for amplifying the relay signal to a target signal, which oscillates between the high target level and the low target level.
Claims12
An amplifying method of a clock signal of an liquid crystal display (LCD) driving circuit, for amplifying a periodic clock signal swinging between a first original level and a second original level to a target signal swinging between a first target level and a second target level, wherein the first original level is higher than the second original level, the first target level is higher than the second target level, the first target level is higher than the first original level, and the second target level is lower than the second original level, the amplifying method for a clock signal of an LCD driving circuit comprising:
- amplifying the clock signal to a relay signal that swings between a first relay level and a second relay level, wherein the first relay level is higher than the second relay level;
- and
- amplifying the relay signal to the target signal, wherein the first relay level is between the first original level and the first target level, the second relay level is between the second original level and the second target level.
A driving stage for an LCD driving circuit, the driving stage being part of the LCD driving circuit in a cascade fashion, the driving stage comprising:
- a clock input terminal, for receiving a clock signal having one of a first original level and a second original level;
- a level shifter, coupling to the clock input terminal, for receiving the clock signal from the clock input terminal, operating at a first target level and a second target level, for amplifying the clock signal to a relay signal having a first relay level and a second relay level;
- and
- an output buffer, coupling to the level shifter, for receiving the relay signal from the level shifter, operating at the first target level and the second target level, for amplifying the relay signal having one of the first target level and the second target level,
- wherein the first original level is higher than the second original level, the first target level is higher than the second target level, the first relay level is between the first original level and the first target level, and the second relay level is between the second original level and the second target level.
Dependencies are inferred from the claim text.