Self-scanning light-emitting element array chip
AssigneeNippon Sheet Glass Co., Ltd.
InventorSeiji Ohno
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Abstract
Provided is a self-scanning light-emitting element array chip structured on a substrate using Si. A lattice mismatching buffer layer (32) is formed on a Si substrate (30). On the lattice mismatching buffer layer (32), successively stacked are an n-type AlGaAs layer (14), a p-type AlGaAs layer (16), an n-type AlGaAs layer (18), and a p-type AlGaAs layer (20) in this order. On the AlGaAs layer (20) provided is an anode electrode (22), on the AlGaAs layer (18) a gate electrode (24), on the bottom surface of the GaAs substrate a cathode electrode (26).
Claims14
A self-scanning light-emitting element array chip, comprising:
- a Si substrate;
- and
- a self-scanning light-emitting element array including pnpn layers formed on the Si substrate.
A self-scanning light-emitting element array chip, comprising:
- a Si substrate;
- a lattice mismatching buffer layer formed on the Si substrate;
- and
- a self-scanning light-emitting element array including pnpn layers formed on the lattice mismatching buffer layer.
A self-scanning light-emitting element array chip, comprising:
- a Si substrate;
- a lattice mismatching buffer layer formed on a part of the Si substrate;
- a self-scanning light-emitting element array including pnpn layers formed on the lattice mismatching buffer layer;
- and
- a driver circuit formed on the Si substrate.
Dependencies are inferred from the claim text.