Method of fabricating local sonos type gate structure and method of fabricating nonvolatile memory cell having the same

Abstract

There is provided a method of fabricating a local SONOS type gate structure and a method of fabricating a nonvolatile memory cell having the same. The method includes forming a gate dielectric layer on a semiconductor substrate. A gate pattern, including a gate electrode and a hard mask layer pattern which are sequentially stacked, is formed on the gate dielectric layer. Then, a recess is formed on the boundary of the gate pattern and the gate dielectric layer. The recess is formed on one side wall of the gate pattern, and is prevented from forming on the other side wall of the gate pattern. A tunnel layer and a trapping dielectric layer are sequentially formed on substantially the entire surface of the semiconductor substrate having the recess formed thereon to fill the recess. At least a portion of the trapping dielectric layer is formed inside the recess.

Dependencies are inferred from the claim text.