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US 2005/0037571 A1Published application
Fowler-Nordheim block alterable EEPROM memory cell
AssigneeAtmel Corporation
InventorBohumil Lojek
Life of this patent
Estimating the term…
Abstract
A block alterable memory cell has a select control gate extending from a floating gate region to a drain region. The block alterable memory cell comprises a substrate layer that further includes a source implant region, an active region, a floating gate transistor region, and a drain implant region. A tunnel oxide layer overlies the substrate layer and is deposited to a thickness of approximately 70 angstroms. The select control gate comprises a first oxide layer overlying the tunnel oxide layer, an inter poly layer overlying over the first oxide layer, and a second layer extending over the floating gate transistor region and the active region to an edge of the drain implant region.
Claims25
A method for manufacturing a block alterable memory cell, such method comprises the following steps:
- depositing a screen oxide over a substrate layer;
- depositing a mask implant layer over the screen oxide layer;
- implanting memory cells in the portion of the substrate layer not covered by the mask implant layer;
- etching a screen oxide and an initial gate oxide from memory cells;
- depositing tunnel window mask;
- etching a tunnel oxide layer;
- depositing control poly layer;
- and
- implanting source and drain regions.
6 more elements
A block alterable memory cell, comprising:
- a substrate layer having a source implant region, a buried implant region essentially contiguous with said source implant region, a tunnel diode window region within said buried implant region, an active region, a floating gate transistor region essentially contiguous with said active region, and a drain implant region;
- a tunnel oxide layer overlaying a portion of said buried implant region;
- a floating gate oxide layer overlaying said floating gate transistor region exclusive of said tunnel diode window region;
- a first layer overlaying said tunnel oxide layer and said floating gate oxide layer;
- an interpoly layer overlaying said first layer and said active region, said interpoly layer extending continuously from an edge of said source implant region to an edge of said drain implant region;
- and
- a second layer extending continuously over said floating gate transistor region and said active region, said second layer extending from an edge of said source implant region to an edge of said drain implant region.
4 more elements
(canceled)
A semiconductor memory device, comprising:
- a memory array arranged into a plurality of rows and a plurality of columns, said memory array further comprising a plurality of block alterable memory cells, each block alterable memory cell having a substrate layer with a source implant region, an active region, a floating gate transistor region, a drain implant region, a tunnel oxide layer overlaying a portion of said substrate layer, a first layer overlaying said tunnel oxide layer, an inter interpoly layer overlaying said first layer, and a second layer extending over said floating gate transistor region and said active region to an edge of said drain implant region;
- an input/output port in communication with said memory array;
- and
- a controller coupled to said input/output port and said memory array.
1 more element
A block alterable memory cell, comprising:
- a substrate layer having a source doped region, a buried doped region essentially contiguous with said source doped region, a tunnel diode window region within said buried doped region, an active region, a floating gate transistor region essentially contiguous with said active region, and a drain doped region;
- a tunnel oxide layer overlaying a portion of said buried doped region;
- a floating gate oxide layer overlaying said floating gate transistor region exclusive of said tunnel diode window region;
- a first layer overlaying said tunnel oxide layer and said floating gate oxide layer;
- an interpoly layer overlaying said first layer and said active region, said interpoly layer extending continuously from an edge of said source doped region to an edge of said drain doped region;
- and
- a second layer extending continuously over said floating gate transistor region and said active region, said second layer extending from an edge of said source doped region to an edge of said drain doped region.
4 more elements
(canceled)
A semiconductor memory device, comprising:
- memory array arranged into a plurality of rows and a plurality of columns, said memory array further comprising a plurality of block alterable memory cells, each block alterable memory cell having a substrate layer with a source doped region, an active region, a floating gate transistor region, a drain doped region, a tunnel oxide layer overlaying a portion of said substrate layer, a first layer overlaying said tunnel oxide layer, an interpoly layer overlaying said first layer, and a second layer extending over said floating gate transistor region and said active region to an edge of said drain doped region;
- an input/output port in communication with said memory array;
- and
- a controller coupled to said input/output port and said memory array.
1 more element
A semiconductor memory device, comprising:
- a memory array arranged into a plurality of rows and a plurality of columns, said memory array further comprising a plurality of block alterable memory cells, each block alterable memory cell having a substrate layer with a source doped region, an active region, a floating gate transistor region, a drain doped region, a tunnel oxide layer overlaying a portion of said substrate layer, a first layer overlaying said tunnel oxide layer, an interpoly layer overlaying said first layer, and a second layer extending over said floating gate transistor region and said active region to an edge of said drain doped region;
- and
- an input/output port in communication with said memory array.
An abutting pair of block alterable memory cells, each memory cell comprising:
- a substrate layer having a source implant region, a buried implant region essentially contiguous with said source implant region, a tunnel diode window region within said buried implant region, an active region, a floating gate transistor region essentially contiguous with said active region, and a drain implant region;
- a tunnel oxide layer overlaying a portion of said buried implant region;
- a floating gate oxide layer overlaying said floating gate transistor region exclusive of said tunnel diode window region;
- a first layer overlaying said tunnel oxide layer and said floating gate oxide layer;
- an end tour poly layer overlaying said first layer and said active region, said interpoly layer extending continuously on from an edge of said source implant region to an edge of said drain implant region;
- and
- a second layer extending continuously on over said floating gate transistor region and said active region, said second layer extending from an edge of said source implant region to an edge of said drain implant region.
4 more elements
An abutting pair of block alterable memory cells, each memory cell comprising:
- a substrate layer having a source doped region, a buried doped region essentially contiguous with said source doped region, a tunnel diode window region within said buried doped region, an active region, a floating gate transistor region essentially contiguous with said active region, and a drain doped region;
- a tunnel oxide layer overlaying a portion of said buried doped region;
- a floating gate oxide layer overlaying said floating gate transistor region exclusive of said tunnel diode window region;
- a first layer overlaying said tunnel oxide layer and said floating gate oxide layer;
- an end tour poly layer overlaying said first layer and said active region, said interpoly layer extending continuously on from an edge of said source doped region to an edge of said drain doped region;
- and
- a second layer extending continuously on to over said floating gate transistor region and said active region, said second layer extending from an edge of said source doped region to an edge of said drain doped region.
4 more elements
Dependencies are inferred from the claim text.