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US 2005/0037522 A1Published application
Dummy fill for integrated circuits
AssigneePraesagus, Inc., a Massachusetts corporation
InventorsTaber Smith, Vikas Mehrotra, David White
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Abstract
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
Claims76
A method comprising
- based on electrical impact analysis and a pattern dependent model of a chemical mechanical polishing process, generating a strategy for placement of dummy fill in an integrated circuit, and
- using the pattern dependent model and the electrical impact analysis to evaluate expected results of the placement of dummy fill in the integrated circuit,
- the use of the model and the electrical impact analysis being embedded as part of the generation of the dummy fill placement strategy,
- the chemical mechanical polishing process comprising one or more steps that are steps of a fabrication process flow, the fabrication process flow comprising two or more steps of fabrication.
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Dependencies are inferred from the claim text.