Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same

An integrated circuit semiconductor device comprising:

• a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern;
• an overlay key region formed in a second portion of the silicon substrate, the overlay key region including a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern by correcting overlay and alignment errors using the second insulating pattern;
• and
• an alignment key region formed in a third portion of the silicon substrate, the alignment key region including a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer filled in the third trench, and a third conductive pattern formed over the second buried insulating layer and the silicon substrate.

A method of fabricating an integrated circuit semiconductor device, the method comprising:

• forming a first buried insulating layer and a second buried insulating layer in a first trench in a cell region and an alignment key region trench of an alignment key region, respectively, of a silicon substrate;
• forming a first insulating pattern and a second insulating pattern in the cell region and an overlay key region, respectively, of the silicon substrate;
• covering the cell region with a first photoresist pattern;
• forming a second trench and a third trench by etching the silicon substrate in the overlay key region and the alignment key region, respectively, by using the first photoresist pattern, the second insulating pattern and the second buried insulating layer as a mask;
• forming a conductive layer over the entire surface of the silicon substrate including the cell region, the overlay key region, and the alignment key region;
• forming a second photoresist pattern over the conductive layer by using the third trench formed in the alignment key region as an alignment key and using the second insulating pattern as an overlay key;
• and
• forming a conductive pattern by patterning the conductive layer using the second photoresist pattern as a mask, the conductive pattern formed by correcting overlay and alignment errors using the second insulating pattern.

A method of fabricating an integrated circuit semiconductor device, the method comprising:

• forming a first buried insulating layer and a second buried insulating layer in a first trench in a cell region and an alignment key region trench in an alignment key region, respectively, of a silicon substrate;
• forming a first insulating pattern and a second insulating pattern in the cell region and an overlay key region, respectively, of the silicon substrate;
• covering the cell region and the alignment key region with a first photoresist pattern;
• forming a second trench by etching the silicon substrate in the overlay key region by using the first photoresist pattern and the second insulating pattern as a mask;
• forming a conductive layer over the entire surface of the silicon substrate including the cell region, the overlay key region, and the alignment key region;
• forming a second photoresist pattern over the conductive layer by using the alignment key region trench formed in the alignment key region as an alignment key and using the second insulating pattern as an overlay key;
• and
• forming a conductive pattern by patterning the conductive layer using the second photoresist pattern as a mask, the conductive pattern formed by correcting overlay and alignment errors using the second insulating pattern.

A method of fabricating an integrated circuit semiconductor device comprising:

• forming at least one trench in a semiconductor substrate;
• forming an insulating pattern over the semiconductor substrate;
• forming a conductive layer over the insulating pattern;
• forming a photoresist pattern over the conductive layer using a step difference between the trench and the insulating pattern so that the insulating pattern functions as an overlay key;
• and
• etching the conductive layer using the photoresist pattern as a mask.