US 2005/0030809 A1 · Sensing circuit for a semiconductor memory

Abstract

A sensing circuit for a semiconductor memory comprising a circuit branch intended to be electrically coupled to a memory bit line having connected thereto a memory cell to be sensed. A bit line precharge circuit is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, depending on a difference between a memory bit line potential and the predetermined bit line potential. At least the precharge circuit includes a precharge negative feedback control loop, for controlling the memory bit line potential during the precharge phase. A same circuit element is provided that controls the memory bit line potential during the precharge phase and evaluates the electric quantity during the evaluation phase of the memory cell sensing operation.

Claims31

Dependent claims

A sensing circuit for a semiconductor memory, comprising:

a circuit branch intended to be electrically coupled to a memory bit line, said memory bit line having connected thereto a memory cell to be sensed;
a bit line precharge circuit, for precharging the memory bit line coupled to the circuit branch to a predetermined bit line potential in a precharge phase of a memory cell sensing operation, and
an evaluation circuit for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation, said electric quantity being indicative of an information content of the memory cell,
characterized in that
the bit line precharge circuit is adapted to both charging and discharging the memory bit line, depending on a difference between a memory bit line potential and the predetermined bit line potential;
at least said bit line precharge circuit includes a precharge negative feedback control loop, for controlling the memory bit line potential during the precharge phase, and
a same circuit element is provided that controls the memory bit line potential during the precharge phase and evaluates the electric quantity during the evaluation phase of the memory cell sensing operation.

4 more elements

A sensing circuit, comprising:

an output node;
an input node adapted to be directly coupled to a memory bit line, with a memory cell to be sensed being coupled to the bit line;
and
a plurality of electronic components, the components being operable in a precharge mode to precharge the bit line to a precharge voltage and the same components being operable in a sensing mode to sense a voltage on the bit line and generate an output voltage on the output node indicating a logic state of data stored in the memory cell.

1 more element

Dependencies are inferred from the claim text.

Sensing circuit for a semiconductor memory

Life of this patent

Sensing circuit for a semiconductor memory

Life of this patent

Abstract

Claims31