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US 2005/0030804 A1Published application
Reduced size plate layer improves misalignments in CUB DRAM
OwnerToshiyuki Nagata, Hiroyuki Yoshida +2inventors
InventorsToshiyuki Nagata, Hiroyuki Yoshida, Masayuki Moroi, Atsushi Satoh
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Abstract
In a DRAM array using a capacitor-under-bitline (CUB) layout, the plate layer of the capacitor is significantly reduced in area to reduce misalignments in connections between the bitline and the underlying transistors.
Claims3
1-5. (canceled)
A method of forming an array of capacitors in a capacitor-under-bitline configuration, comprising the step of forming a conductive plate layer over a partially fabricated array of capacitors;
- wherein said plate layer is not a critical alignment factor, and wherein further components of said capacitor array are not aligned to said plate layer.
A method for fabricating a pit-type DRAM memory cell array, comprising the actions of:
- forming a plurality of transistor gates;
- forming a plurality of pit-type capacitors which are aligned to said gates;
- forming a plurality of bit line contacts, which are aligned to said capacitors;
- wherein a plate layer is also connected to one node of said capacitors, but alignment of said bit line contact does not depend on the alignment of said plate layer.
1 more element
Dependencies are inferred from the claim text.