Memory module including an integrated circuit device

A memory module comprising:

• a plurality of memory devices;
• and
• an integrated circuit device, coupled to the plurality of memory devices, the integrated circuit device including:
• a first circuit to receive:
• control information specifying a write operation;
• and
• address information specifying a memory location corresponding to the write operation, wherein the memory location is in a first memory device of the plurality of memory devices, and wherein the control information and the address information are received in a multiplexed format;
• and
• a second circuit, including a plurality of output drivers, to output data after a first number of clock cycles of an external clock signal transpire, wherein the data is to be written to the first memory device during the write operation.

A method of operation in a memory module that includes a plurality of memory devices and an integrated circuit device, the method comprising:

• receiving at pins of the integrated circuit device, in a multiplexed format, control information and address information, the control information specifying a write operation, and the address information specifying a location within a memory array for the write operation, wherein the memory array is located on a first memory device of the plurality of memory devices;
• outputting to the memory device, an operation code that corresponds to the write operation;
• and
• receiving at pins of the first memory device, data to be written to the memory array during the write operation, after a predetermined number of clock cycles of an external clock signal transpire, wherein the data is received in response to the operation code.

A memory module comprising:

• a plurality of memory devices including a first memory device;
• and
• an integrated circuit device, coupled to the plurality of memory devices, the integrated circuit device including:
• means for receiving control information and address information in a multiplexed format, the control information specifying a write operation, and the address information specifying a memory location in the first memory device for the write operation;
• means for outputting an operation code, corresponding to the write operation, to the memory device;
• and
• means for outputting data after a predetermined number of clock cycles of an external clock signal transpire from outputting the operation code, wherein the data is to be written to the memory array during the write operation.