Method of generating an enable signal of a standard memory core and relative memory device

A method for generating an enable signal in a memory device selectably accessible with an LPC or an SPI serial communication protocol or with an A/AMUX parallel communication protocol, the memory device comprising first, second and third pins;

• a memory core;
• a multi-protocol interface coupled to an external data bus, to an external address bus, to the first pin for receiving a timing signal, to the second pin for receiving a first start signal of one of the serial communication protocols or of the parallel communication protocol;
• and an internal data bus and an internal address bus for transferring data and addresses between the memory core and the multi-protocol interface;
• the multi-protocol interface comprising a decoding circuit for the serial communication protocols and the parallel communication protocol, the decoding circuit coupled to the external data bus, to the external address bus, to the first and third pins, and having an input for receiving a logic configuration signal, and exchanging with the memory core data and addresses through the internal data and address busses;
• the method comprising:
• generating the logic configuration signal for the multi-protocol interface for selecting between the LPC and SPI serial communication protocols;
• providing the logic selection signal via the third pin to the multi-protocol interface for the parallel communication protocol, with memory addresses to be accessed based upon the parallel communication protocol through the external address bus and with the address multiplexing signal provided via the first pin for the parallel communication protocol;
• and
• generating the enable signal for the memory core as a logic combination of the logic selection signal, of the logic configuration signal, of the first start signal of one of the serial communication protocols or of the parallel communication protocol, and of an internally generated second start signal that is active during execution of the serial communication protocol.

A method for generating an enable signal in a memory device selectably accessible between two distinct serial communication protocols and between a parallel communication protocol, the memory device comprising first, second and third pins;

• a memory core;
• a multi-protocol interface coupled to an external data bus, to an external address bus, to the first pin for receiving a timing signal, to the second pin for receiving a first start signal of one of the serial communication protocols or of the parallel communication protocol;
• and an internal data bus and an internal address bus for transferring data and addresses between the memory core and the multi-protocol interface;
• the method comprising:
• generating a logic configuration signal for the multi-protocol interface for selecting between the two distinct serial communication protocols;
• providing a logic selection signal via the third pin to the multi-protocol interface for the parallel communication protocol, with memory addresses to be accessed based upon the parallel communication protocol through the external address bus and with an address multiplexing signal provided via the first pin for the parallel communication protocol;
• and
• generating the enable signal for the memory core as a logic combination of the logic selection signal, of the logic configuration signal, of the first start signal of one of the serial communication protocols or of the parallel communication protocol, and of an internally generated second start signal that is active during execution of the serial communication protocol.

A memory device comprising

• first, second and third pins;
• a memory core;
• a multi-protocol interface coupled to an external data bus, to an external address bus, to said first pin for receiving a timing signal, and to said second pin for receiving a first start signal of one of two distinct serial communication protocols or of a parallel communication protocol;
• a configuration circuit for generating a logic configuration signal for said multi-protocol interface for selecting between the two distinct serial communication protocols;
• and
• an internal data bus and an internal address bus for transferring data and addresses between said memory core and said multi-protocol interface;
• said multi-protocol interface receiving a logic selection signal via said third pin for the parallel communication protocol, with memory addresses to be accessed based upon the parallel communication protocol through the external address bus, and with an address multiplexing signal being received via said first pin for the parallel communication protocol, and generating the enable signal for said memory core as a logic combination of the logic selection signal, of the logic configuration signal, of the first start signal of one of the serial communication protocols or of the parallel communication protocol, and of an internally generated second start signal that is active during execution of the serial communication protocol, said multi-protocol interface comprising
• a decoding circuit for the serial communication protocols and the parallel communication protocol, said decoding circuit coupled to the external data bus, to the external address bus, to said first and third pins and having an input for receiving the logic configuration signal, and exchanging with said memory core data and addresses through said internal data and address busses.

A memory device comprising

• first, second and third pins;
• a memory core;
• a multi-protocol interface coupled to an external data bus, to an external address bus, to said first pin for receiving a timing signal, and to said second pin for receiving a first start signal of one of two distinct serial communication protocols or of a parallel communication protocol;
• a configuration circuit for generating a logic configuration signal for said multi-protocol interface for selecting between the two distinct serial communication protocols;
• and
• an internal data bus and an internal address bus for transferring data and addresses between said memory core and said multi-protocol interface;
• said multi-protocol interface receiving a logic selection signal via said third pin for the parallel communication protocol, with memory addresses to be accessed based upon the parallel communication protocol through the external address bus, and with an address multiplexing signal being received via said first pin for the parallel communication protocol, and generating the enable signal for said memory core as a logic combination of the logic selection signal, of the logic configuration signal, of the first start signal of the serial communication protocol or of the parallel communication protocol, and of an internally generated second start signal that is active during execution of the serial communication protocol.