Logical data block, magnetic random access memory, memory module, computer system and method
AssigneeHewlett-Packard Development Company, L.P.
InventorsKenneth Smith, Frederick Pemer, Richard Hilton
Life of this patent
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Abstract
A logical data block in a MRAM is disclosed. The logical data block comprises magnetic memory cells formed at intersections of hard-axis generating conductors and an easy-axis generating conductor. The logical data block may further be configured in size by a preselected, block-based error correction code. A magnetic memory module and computer system including a MRAM having a logical data block according to embodiments of the present invention are also disclosed. Additionally, a method embodiment of reducing half-select write errors within a MRAM is disclosed.
Claims23
A logical data block in a magnetic random access memory (MRAM), the logical data block comprising magnetic memory cells formed at intersections of hard-axis generating conductors and an easy-axis generating conductor, wherein the logical data block is configured in size by a preselected, block-based error correction code.
A magnetic random access memory (MRAM) comprising:
- a plurality of logical data blocks, wherein each logical data block comprises:
- an easy-axis generating conductor;
- a plurality of hard-axis generating conductors;
- a plurality of magnetic memory cells formed at intersections of the easy-axis conductor and the plurality of hard-axis conductors;
- and
- each logical data block comprising a size according to a preselected, block-based error correction code.
A magnetic memory module, comprising:
- at least one magnetic random access memory (MRAM) comprising:
- at least one logical data block, comprising:
- a plurality of magnetic memory cells;
- an easy-axis conductor configured for generating an easy-axis magnetic field, operably coupled to a first side of each of the plurality of magnetic memory cells;
- and
- a plurality of hard-axis conductors configured for generating a hard-axis magnetic field operably coupled to a second side of each of the plurality of magnetic memory cells.
A computer system, comprising:
- an input device;
- an output device;
- a processor device operably coupled to the input device and the output device;
- and
- a memory device operably coupled to the processor device, the memory device comprising:
- at least one magnetic random access memory (MRAM) comprising:
- at least one logical data block, comprising:
- an easy-axis conductor configured for generating an easy-axis magnetic field;
- a plurality of hard-axis conductors configured for generating a hard-axis magnetic field;
- and
- magnetic memory cells formed at intersections between the easy-axis conductor and the plurality of hard-axis conductors.
A method of reducing half-select write errors within a magnetic random access memory (MRAM), comprising:
- providing an MRAM having at least one logical data block, wherein each logical data block comprises:
- an easy-axis generating conductor;
- a plurality of hard-axis generating conductors;
- and
- a plurality of magnetic memory cells formed at intersections of the easy-axis conductor and the plurality of hard-axis conductors.
Dependencies are inferred from the claim text.