Controlling circuit for a pulse width modulated DC/DC converter

A controlling circuit, comprising:

• a front-stage circuit generating an output signal in response to a control of an input voltage, a switch signal and a modulation signal;
• a comparator electrically connected to said front-stage circuit for comparing said output signal from said front-stage circuit with an output signal from a current amplifier and generating a reset signal in response to a compared result;
• a latch circuit electrically connected to said comparator for generating an output signal in response to a control of said reset signal and a set signal;
• a clock generator electrically connected to said front-stage circuit and said latch circuit to generate said modulation signal and said set signal, wherein said set signal has a first waveform with a first low-potential pulse while in a heavy-load state to prevent said reset signal from changing in response to said output signal from said latch circuit while said set signal functions, for preventing an error operation of said converter resulting from erroneously comparing an output signal from said front-stage circuit with said output signal from said current amplifier, and said set signal has a second waveform with a second low-potential pulse while in a light-load state to set a minimum time of operation for driving said converter into a power-saving mode;
• a driving circuit electrically connected to said latch circuit and generating a driving signal in response to said output signal from said latch circuit, so as to drive a switch to generate a switch signal for controlling said current amplifier and a step-down circuit;
• and
• a differential amplifier electrically connected to said step-down circuit and generating an output signal in response to a control of an output voltage from said step-down circuit and a reference voltage.

A controlling circuit, comprising:

• a front-stage circuit generating an output signal in response to a control of an input voltage, a switch signal and a modulation signal;
• a comparator electrically connected to said front-stage circuit for comparing said output signal from said front-stage circuit with an output signal from a current amplifier and generating a reset signal in response to a compared result;
• a latch circuit electrically connected to said comparator for generating an output signal in response to a control of said reset signal and a set signal;
• a clock generator electrically connected to said front-stage circuit and said latch circuit to generate said modulation signal and said set signal, wherein said set signal has a first waveform with a first low-potential pulse while in a heavy-load state to prevent said reset signal from changing in response to said output signal from said latch circuit while said set signal functions, for preventing an error operation of said converter resulting from erroneously comparing an output signal from said front-stage circuit with said output signal from said current amplifier, and said set signal has a second waveform with a second low-potential pulse while in a light-load state to set a minimum time of operation for driving said converter into a power-saving mode;
• a post-stage circuit electrically connected to said latch circuit and generating said switch signal in response to said output signal from said latch circuit for controlling said front-stage circuit;
• and
• a differential amplifier electrically connected to said post-stage circuit and generating an output signal in response to a control of an output voltage from said post-stage circuit and a reference voltage.