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AssigneeInternational Business Machines Corporation
InventorsHuajie Chen, Dureseti Chidambarrao, Oleg Gluschenkov, An Steegen, Haining Yang
Estimating the term…
A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
An integrated circuit having complementary metal oxide semiconductor (CMOS) transistors including a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), said PFET and said NFET each having a channel region and source and drain regions disposed in a first semiconductor region having a first composition, wherein a first strain is applied to said channel region of said PFET but not to said channel region of said NFET via second semiconductor regions having a second composition lattice-mismatched to said first semiconductor region, said second semiconductor regions underlying said source and drain regions of said PFET but not underlying said channel region of said PFET and not underlying said NFET.
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An integrated circuit having complementary metal oxide semiconductor (CMOS) transistors including a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), the NFET and the PFET each having a channel region and source and drain regions disposed in a first semiconductor region consisting essentially of silicon, wherein a first strain is applied to the channel region of the PFET but not to the channel region of the NFET via buried lattice-mismatched semiconductor regions consisting essentially of silicon germanium in underlying the source and drain regions of the PFET but not underlying the channel region of the PFET and not underlying the NFET, said silicon germanium of said buried lattice-mismatched semiconductor regions having proportions-a composition according to the formula SixGey where x and y are percentages each being at least one percent, x plus y equaling 100 percent.
A method of fabricating a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), said NFET and said PFET each having a channel region, said channel region of said PFET having a first strain and said channel region of said NFET not having said first strain, said method comprising:
Dependencies are inferred from the claim text.