US 2004/0234233 A1Published application

Jitter correcting apparatus and method for video signals

AssigneeSamsung Electronics Co., Ltd.

InventorLee Jesuk

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Abstract

A jitter correcting apparatus and method for a video signal in a video signal reproduction system includes a digital video decoder for demodulating an externally-applied video signal and a phase-locked loop for generating a first clock signal synchronized with the video signal. The system includes an address generator, a comparator and a dual port memory device. The address generator generates a write address for writing the video signal in response to the first clock signal, generates a read address for reading the video signal in response to a second clock signal having a fixed frequency, and corrects the write and read addresses in response to a head switching signal and first and second comparison signals. The comparator compares the write address with the read address and generates the first comparison signal and the second comparison signal according to a result of the comparison. The dual port memory device stores the video signal at a location corresponding to the write address in response to the first clock signal and outputs a video signal stored at a location corresponding to the read address in response to the second clock signal. Accordingly, the jitter of a video signal, which may occur while processing an analog video signal in a digital mode, is corrected using a memory device having a small capacity, thereby allowing a video image to be stably output.

Claims13

Dependent claims

A jitter correcting apparatus for correcting jitter of an input video signal in a video signal reproduction system including a digital video decoder for demodulating a luminance signal of the video signal in response to a first clock signal having a variable frequency and for demodulating a chrominance signal of the video signal in response to a second clock signal of a fixed frequency, the jitter correcting apparatus comprising:

a luminance signal address generator for generating a luminance signal write address for writing the luminance signal in response to the first clock signal, for generating a luminance signal read address for reading the luminance signal in response to the second clock signal, for comparing the luminance signal write address with the luminance signal read address, and for correcting the luminance signal read and write addresses based on a result of the comparison;
a first dual port memory device for storing the luminance signal at a location corresponding to the luminance signal write address in response to the first clock signal and for outputting the luminance signal stored at a location corresponding to the luminance signal read address in response to the second clock signal;
a chrominance signal address generator for generating a chrominance signal write address for writing the chrominance signal and a chrominance signal read address for reading the chrominance signal, in response to the second clock signal, for comparing the chrominance signal write address with the chrominance signal read address, and for correcting the chrominance signal read and write addresses based on a result of the comparison;
and
a second dual port memory device for storing the chrominance signal at a location corresponding to the chrominance signal write address and for outputting the chrominance signal stored at a location corresponding to the chrominance signal read address, in response to the second clock signal.

2 more elements

A method for correcting jitter of an input video signal comprising a chrominance signal, a luminance signal and horizontal and vertical synchronizing signals, during writing of the video signal into corresponding dual port memory devices and reading of the written video signal, the method comprising the steps of:

(a) generating luminance and chrominance signal write addresses in response to a first clock signal having a variable frequency or in response to a second clock signal having a fixed frequency and generating luminance and chrominance signal read addresses in response to the second clock signal;
(b) correcting a horizontal cycle of the video signal and generating an error value corresponding to the average skew of a field of the video signal;
(c) resetting the luminance and chrominance signal read addresses when a head switching signal is generated in response to the error value to compensate for accumulated errors between write addresses and read addresses;
(d) determining approach states between the luminance and chrominance signal write addresses and the luminance and chrominance signal read addresses, respectively, after step (c), and correcting the write addresses or the read addresses;
and
(e) writing and reading the video signal in response to the corrected luminance and chrominance signal write and read addresses.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/874,073Filed 22 Jun 2004
Priority: KR 99-983523 Mar 1999
Published: 25 Nov 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

H04N 9/896
Time-base error compensation: using a digital memory with independent write-in and read-out clock generators
H04N 5/78263
Involving helical scanning of the magnetic tape: for recording on tracks inclined relative to the direction of movement of the tape
H04N
Pictorial communication

Family

Application09/532,178Division · filed 20 Mar 2000
Application10/874,073Division · filed 22 Jun 2004
US 6,801,706 B1Related patent
US 7,212,724 B2Related patent
US 2004/0234233 A1This patent

From the US filing history. Foreign family members aren’t listed.