Logic circuits for performing threshold functions

A logic circuit for generating four binary outputs as four threshold functions of four binary inputs to the logic circuit, the threshold functions comprising a first threshold function which is high if at least one of the binary inputs is high, a second threshold function which is high if at least two of the binary inputs are high, a third threshold function which is high if at least three of the binary inputs are high, and a fourth threshold function which is high if all of the binary inputs are high, the logic circuit comprising:

• first level logic comprising two logic parts, each logic part comprising a NOR gate and a NAND gate and having two first level inputs for receiving the binary inputs and two first level outputs;
• and
• second level logic comprising four second level outputs, four second level inputs for receiving second level binary inputs and connected to the four first level outputs, a NAND gate, a first gate generating logical AND combinations of two pairs of second level binary inputs and NOR combining the logical AND combinations, a second gate generating logical OR combinations of two pairs of second level binary inputs and NAND combining the logical OR combinations, and a NOR gate;
• wherein one of said four binary outputs is generated at each of said four outputs.

A logic circuit for generating three binary outputs as three threshold functions of binary inputs to the logic circuit, the threshold functions comprising a first threshold function which is high if at least one of the binary inputs is high, a second threshold function which is high if at least two of the binary inputs are high, and a third threshold function which is high if all of the binary inputs are high, the logic circuit comprising:

• first level logic comprising two logic parts, a first logic part comprising a NOR gate and a NAND gate and having two first level inputs for receiving two of the binary inputs and two first level outputs, and a second logic part comprising an inverter having one first level logic input for receiving one of the binary inputs and one first level output;
• and
• second level logic comprising three second level outputs, and three second level inputs for receiving second level binary inputs and connected to the three first level outputs, a NAND gate, a gate generating a logical AND combination of two second level binary inputs and NOR combining the logical AND combination with one other second level binary input, and a NOR gate;
• wherein one of said three binary outputs is generated at each of said three outputs.

A logic circuit for generating three binary outputs as three threshold functions of binary inputs to the logic circuit, the threshold functions comprising a first threshold function which is high if at least one of the binary inputs is high, a second threshold function which is high if at least two of the binary inputs are high, and a third threshold function which is high if all of the binary inputs are high, the logic circuit comprising:

• first level logic comprising two logic parts, a first logic part comprising a NOR gate and a NAND gate and having two first level inputs for receiving two of the binary inputs and two first level outputs, and a second logic part comprising an inverter having one first level logic input for receiving one of the binary inputs and one first level output;
• and
• second level logic comprising three second level outputs, and three second level inputs for receiving second level binary inputs and connected to the three first level outputs, a NAND gate, a gate generating a logical OR combination of two second level binary inputs and NAND combining the logical OR combination with one other second level binary input, and a NOR gate;
• wherein one of said three binary outputs is generated at each of said three outputs.