Redundancy register architecture for soft-error tolerance and methods of making the same

A method for providing yield enhancement for a semiconductor memory device comprising:

• providing a plurality of registers individually addressable and forming a plurality of single bit slices of said memory device;
• storing identifying information for redundant single bit slices in each of said registers;
• providing an enable circuit for each of said single bit slices;
• connecting said enable circuit to said plurality of registers in each of said single bit slices;
• designating said enable circuit inactive when said plurality of registers are not in use, such that logic states of said registers are not relevant to said memory device operation;
• and
• designating said enable circuit active when said plurality of registers identifies said redundant single bit slices.

A method of performing yield enhancement in memory devices having a plurality of logic registers for steering memory selection away from single bit slices or rows having defects to spare, redundant single bit slices or rows, said method comprising:

• electrically connecting each of said registers to a corresponding first exclusive OR logic device having inputs and an output;
• serially connecting each of said first exclusive OR logic devices together as a string of logic devices and adapted to provide an exclusive OR logic signal output based upon a comparison of two of said registers;
• connecting a plurality of said string of logic devices to a corresponding second exclusive OR logic devices;
• and
• performing a parity check of said registers by comparing logic states of said second exclusive OR logic devices.