Device and method for configuring a cache tag in accordance with burst length
AssigneeMicron Technology, Inc.
InventorJoseph T. Pawlowski
Life of this patent
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Abstract
In a cache tag integrated on an SRAM with a memory cache, laser fuses are programmed to indicate which, if any, tag subarrays in the cache tag are not functioning properly. In addition, the burst length of the SRAM is increased to reduce the number of tag subarrays necessary for operation of the cache tag so any non-functional tag subarrays are no longer necessary. In accordance with the indications from the programmed laser fuses and the increased burst length, logic circuitry disables any non-functional tag subarrays, leaving only functional tag subarrays to provide tag functionality for the memory cache. As a result, an SRAM that is typically scrapped as a result of non-functional tag subarrays can, instead, be recovered for sale and subsequent use.
Claims37
An electronic system comprising a microprocessor operably coupled to a main memory, a cache memory, a cache tag, the cache tag comprising:
- a plurality of tag subarrays;
- and
- enabling circuitry coupled to the plurality of tag subarrays configured for selectively enabling the plurality of tag subarrays in accordance with a selected burst length of the cache tag and a functional status of the plurality of tag subarrays.
A semiconductor device, comprising:
- a plurality of memory arrays;
- and
- enabling circuitry coupled to the plurality of memory arrays configured for selectively enabling the plurality of memory arrays in accordance with a selected burst length indicated by a burst length signal and a functional status of the plurality of memory arrays.
A semiconductor device, comprising:
- a cache memory;
- and
- a cache tag, the cache tag including:
- a plurality of tag subarrays;
- and
- enabling circuitry coupled to the plurality of tag subarrays for selectively enabling the plurality of tag subarrays in accordance with a selected burst length of the cache memory and a functional status of the plurality of tag subarrays.
A method for repairing a semiconductor memory device having a cache tag including at least one nonfunctional tag subarray, the method comprising:
- increasing a selected burst length of the semiconductor memory device so the at least one nonfunctional tag subarray is not needed for operation of the semiconductor memory device;
- and
- selectively disabling the at least one nonfunctional tag subarray.
A method for repairing a semiconductor memory device having a cache tag including at least one nonfunctional tag subarray and at least one functional tag subarray, the method comprising:
- programming at least one status indicating element to indicate a functional status of the at least one functional tag subarray;
- increasing a selected burst length of the semiconductor memory device;
- and
- selecting the at least one functional tag subarray in accordance with the at least one status indicating element, the selected burst length, and at least one address signal.
A method for changing a selected burst length of a semiconductor memory device, the method comprising:
- increasing the selected burst length of the semiconductor memory device so at least one nonfunctional tag subarray of the semiconductor memory device are not needed for operation of the semiconductor memory device;
- and
- selectively disabling the at least one nonfunctional tag subarray.
Dependencies are inferred from the claim text.