Limit-cycle-free FIR/IIR halfband digital filter with shared registers for high-speed sigma-delta A/D and D/A converters
AssigneeTexas Instruments Incorporated
InventorZhongnong Jiang
Life of this patent
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Abstract
A multiplexed FIR/IIR digital filter structure (300) which offers linear phase response and low group delay by switching on a FIR filter portion (31) or a IIR filter portion (32). To reduce the silicon area, the FIR/IIR filter (300) shares registers which is enabled because the FIR and IIR processing do not use the registers at the same time but rather consecutively. Further, the multiplexed FIR/IIR digital filter structure (300) can offer limit-cycle-free IIR operation using two's-complement truncation in combination with positive valued allpass coefficients.
Claims16
A limit-cycle free digital filter comprising;
- a finite impulse response filter (FIR) portion having a plurality of delay elements implemented for processing data;
- a infinite impulse response filter (IIR) portion having a plurality of delay elements implemented for processing said data;
- a multiplexer system coupled to said FIR portion and said IIR portion for switching a plurality of shared delay elements therebetween;
- and
- said shared delay elements comprise a portion of said FIR portion delay elements and said IIR filter portion delay elements, wherein said shared delay elements are used consecutively for FIR data processing and IIR data processing.
A limit-cycle free digital filtering system comprising:
- a signal source for generating a digital signal;
- a digital filter having an Nth-order and coupled to said signal source for receiving and filtering said digital signal by performing a sequence of operations including delaying products of said digital signal for each order of said digital filter, said digital filter comprising:
- a finite impulse response filter (FIR) portion having an input for receiving said digital signal and an output for outputting a filtered signal corresponding to said digital signal, said FIR portion further having an NFIRth-order and a plurality of delay elements corresponding to NFIR;
- a infinite impulse response filter (IIR) portion having an input for receiving said digital signals and an output for outputting a filtered signal corresponding to said digital signal, said IIR portion further having an NIIRth-order and a plurality of delay elements corresponding to NIIR;
- a multiplexer system coupled to said FIR portion and said IIR portion for switching a plurality of delay elements therebetween for common use.
Dependencies are inferred from the claim text.