Calculation system of fault coverage and calculation method of the same
AssigneeKabushiki Kaisha Toshiba
InventorYasuyuki Nozuyama
Life of this patent
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Abstract
A calculation system of fault coverage includes a data acquiring module acquiring layout information and gate net data, a layout analysis and fault link module extracting a layout element information and generating a undetected fault list, a fault detecting module generating a detected and undetected fault list, and a weight calculating module adding layout element information as weight, based on a link file between faults and layout element information to be generated based on the layout information, the gate net data, and the detected and undetected fault list.
Claims20
A calculation system of fault coverage comprising:
- a data acquiring module configured to acquire layout information and gate net data of an LSI;
- a layout analysis and fault link module configured to analyze a condition of connection of an input terminal and an output terminal of a basic cell regarding an entire layout based on the layout information and the gate net data, to extract the result of the analysis as layout element information, and to generate an undetected fault list;
- a fault detecting module configured to execute any of fault simulation and an automatic test pattern generation on the undetected fault list and to generate a detected and undetected fault list;
- and
- a weight calculating module configured to add the layout element information corresponding to a fault in the detected and undetected fault list as weight, based on a link file between faults and layout element information to be generated based on the layout information, the gate net data, and the detected and undetected fault list by the layout analysis and fault link module.
A computer-implemented calculation method of fault coverage comprising:
- acquiring layout information and gate net data of an LSI;
- generating a fault list by analyzing a condition of connection of an input terminal and an output terminal of a basic cell regarding an entire layout based on the layout information and the gate net data and extracting the result of the analysis as layout element information;
- executing any of fault simulation and automatic test pattern generation on the fault list and generating a detected and undetected fault list;
- generating a link file between faults and layout element information by use of the layout information, the gate net data, and the detected and undetected fault list;
- and
- adding a layout element corresponding to any one of a detected fault and a undetected fault as weight.
Dependencies are inferred from the claim text.