Method for improving capacitor noise and mismatch constraints in a semiconductor device
AssigneeFreescale Semiconductor, Inc.
InventorPatrick G. Drennan
Life of this patent
Estimating the term…
Abstract
In one embodiment, a method (50) is provided for improving switched capacitor performance by lowering a mismatch constraint to be equal to, or nearly equal to, a noise constraint. The mismatch constraint is lowered by increasing a finger spacing of a fringe capacitor design (10) while maintaining the same surface area covered by the fringe capacitor design (10). In another embodiment, a noise constraint is lowered by decreasing finger spacing. Lowering the noise constraint by decreasing finger spacing reduces the area of a fringe capacitor used in, for example, an analog-to-digital converter. Both embodiments may improve performance of the analog-to-digital converter by lowering power consumption, increasing speed, or both.
Claims20
A method for satisfying a mismatch constraint of a fringe capacitor design comprising the steps of:
- providing a first fringe capacitor design with a predetermined area and a first finger spacing;
- determining a first capacitance value of the first fringe capacitor design to meet the mismatch constraint;
- determining a second capacitance value to meet a MOSFET (metal oxide semiconductor field effect transistor) thermal noise constraint of the first fringe capacitor design;
- determining that the second capacitance value is less than the first capacitance value;
- and
- increasing the finger spacing from the first finger spacing to a second finger spacing while maintaining the same predetermined area to obtain a second fringe capacitor design, wherein the second fringe capacitor design has a lower mismatch constraint than the first fringe capacitor design.
A method for satisfying a noise constraint of a fringe capacitor design comprising the steps of:
- providing a first fringe capacitor design with a first finger spacing;
- determining a first capacitance value of the first fringe capacitor design to meet a mismatch constraint;
- determining a second capacitance value to meet a MOSFET (metal oxide semiconductor field effect transistor) thermal noise constraint of the first fringe capacitor design
- determining that the second capacitance value is greater than the first capacitance value;
- and
- decreasing the finger spacing from the first finger spacing to a second finger spacing to obtain a second fringe capacitor design, wherein the second fringe capacitor design has a lower noise constraint than the first fringe capacitor design.
A method for satisfying a predetermined design constraint of a fringe capacitor design comprising:
- defining the predetermined constraint;
- determining that a first fringe capacitor design having a first finger spacing does not meet the predetermined constraint;
- and
- adjusting the finger spacing from the first finger spacing to a second finger spacing to obtain a second fringe capacitor design having the second finger spacing.
Dependencies are inferred from the claim text.