Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same

The device of claim. 1, wherein said comparator is configured to generate a pair of complementary internal parity signals in response to signals generated by said first XOR circuit.

An integrated circuit device, comprising:

• a data inversion circuit that is configured to evaluate bit differences between first and second ordered groups of data received in parallel at inputs thereof by performing bit-to-bit comparisons between corresponding bits in the first and second ordered groups of data and is further configured to generate a version of the first ordered group of data in parallel with an inverted version of the second ordered group of data at outputs thereof when a number of bit differences between the version of the first ordered group of data and the second ordered group of data is greater than one-half the number of bits of data within the second ordered group of data, said data inversion circuit comprising a plurality of parity signal generators that are configured to generate at least a first external parity signal that identifies whether the version of the first ordered group of data is an inverted or noninverted version of the first ordered group of data.

A data inversion circuit of a semiconductor device with a multiple bit pre-fetch structure, the data inversion circuit comprising:

• a plurality of inversion circuits that in parallel receive a plurality of input data pre-fetched simultaneously with initial input data, perform inversion/non-inversion of the plurality of input data, and generate a plurality of output data,
• wherein the initial input data is output data output during a previous clock cycle and each of the plurality of inversion circuits receives two input data neighboring in an output order among the initial input data and the plurality of input data, determines how many of corresponding bits of the two input data are toggled to each other, and performs inversion/non-inversion for latter one of the two input data according to the determination of how many of the corresponding bits of the two input data are toggled.