Data integrity in protocol offloading
AssigneeSliliquent Technologies Inc.
InventorAmit Oren
Life of this patent
Estimating the term…
Abstract
A method for data verification is provided. An input block of data is received together with a modulo-based input error detection code associated with the input block, the input block comprising a plurality of sub-blocks. A subset of the sub-blocks is selected to be included in an output block. An error correction term is determined based on the selected subset. The selected subset of the sub-blocks is concatenated together with the input error detection code and the error correction term to generate an output block for conveyance to a destination processor.
Claims72
A method for data verification, comprising:
- receiving an input block of data together with a modulo-based input error detection code associated with the input block, the input block comprising a plurality of sub-blocks;
- selecting a subset of the sub-blocks to be included in an output block;
- determining an error correction term based on the selected subset;
- and
- concatenating the selected subset of the sub-blocks together with the input error detection code and the error correction term to generate an output block for conveyance to a destination processor.
A method for error detection, comprising:
- receiving a block of data having a modulo-based input error detection code and an error correction term appended thereto;
- calculating an output error detection code of the block;
- combining the input error detection code and the error correction term to produce a modified error detection code;
- and
- comparing the calculated error detection code to the modified error detection code so as to detect an error in the block.
A method for data processing, comprising:
- receiving an input block of data together with a modulo-based input error detection code associated with the input block, the input block comprising a plurality of input sub-blocks;
- generating one or more protocol-related sub-blocks to be incorporated together with the input sub-blocks in a specified order in an output block for conveyance to a destination processor;
- determining an error correction term based on the specified order of the protocol-related sub-blocks and the input sub-blocks;
- determining a modulo-based output error detection code responsively to the input error detection code and the error correction term;
- and
- concatenating the protocol-related sub-blocks, the input sub-blocks and the output error detection code to generate an output block for conveyance to a destination processor.
A protocol processor, comprising:
- a receiving circuit, adapted to receive an input block of data together with a modulo-based input error detection code associated with the input block, the input block comprising a plurality of sub-blocks;
- a parser, adapted to select a subset of the sub-blocks to be included in an output block;
- a correction term calculator, adapted to determine an error correction term based on the selected subset;
- and
- an aggregator, adapted to concatenate the selected subset of the sub-blocks together with the input error detection code and the error correction term to generate an output block for conveyance to a destination processor.
A data receiver, comprising:
- a receiving circuit, adapted to receive a block of data having a modulo-based input error detection code and an error correction term appended thereto;
- and
- an error detection circuit, which is coupled to compute an output error detection code of the block received by the receiving circuit, to combine the input error detection code and the error correction term to produce a modified error detection code, and to compare the calculated error detection code to the modified error detection code so as to detect an error in the block.
A computer system, comprising:
- a protocol processor, which comprises:
- a receiving circuit, adapted to receive an input block of data together with a modulo-based input error detection code associated with the input block, the input block comprising a plurality of sub-blocks;
- a parser, adapted to select a subset of the sub-blocks to be included in an output block;
- a correction term calculator, adapted to determine an error correction term based on the selected subset;
- and
- an aggregator, adapted to concatenate the selected subset of the sub-blocks together with the input error detection code and the error correction term to generate an output block;
- and
- a destination processor, which is coupled to receive the output block from the protocol processor and to verify the data in the output block responsively to the input error detection code and the error correction term.
A protocol processor, comprising:
- a receiving circuit, adapted to receive an input block of data together with a modulo-based input error detection code associated with the input block, the input block comprising a plurality of input sub-blocks;
- a parser, adapted to generate one or more protocol-related sub-blocks to be incorporated together with the input sub-blocks in a specified order in an output block for conveyance to a destination processor;
- a code calculator, adapted to determine an error correction term based on the specified order of the protocol-related sub-blocks and the input sub-block, and to determine a modulo-based output error detection code responsively to the input error detection code and the error correction term;
- and
- an aggregator, adapted to concatenate the protocol-related sub-blocks, the input sub-blocks and the output error detection code to generate an output block for conveyance to a destination processor.
A computer system, comprising:
- a source processor, which is adapted to generate an input block of data, comprising a plurality of input sub-blocks, and to generate a modulo-based input error detection code for the input block;
- and
- a protocol processor, coupled to receive the input block together with the modulo-based input error detection code, and comprising:
- a parser, adapted to generate one or more protocol-related sub-blocks to be incorporated together with the input sub-blocks in a specified order in an output block for conveyance to a destination processor;
- a code calculator, adapted to determine an error correction term based on the specified order of the protocol-related sub-blocks and the input sub-blocks, and to determine a modulo-based output error detection code responsively to the input error detection code and the error correction term;
- and
- an aggregator, adapted to concatenate the protocol-related sub-blocks, the input sub-blocks and the output error detection code to generate an output block for conveyance to a destination processor.
A computer software product for receiving data, the product comprising a computer-readable medium in which program instructions are stored, which instructions, when read by a computer, cause the computer to receive a block of data having a modulo-based input error detection code and an error correction term appended thereto, to compute an output error detection code of the block, to combine the input error detection code and the error correction term to produce a modified error detection code, and to compare the calculated error detection code to the modified error detection code so as to detect an error in the block.
Dependencies are inferred from the claim text.