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US 2004/0205385 A1Published application
Method and apparatus for improving reliability in microprocessors
AssigneeIntel Corporation
InventorRonald O. Smith
Life of this patent
Estimating the term…
Abstract
A method and system provides an increased robustness and protection against the occurrence of soft errors in parallel connect functional redundancy checking processors. This is achieved by predicting in advance the likely occurrence of a soft error and its impact on the resulting instruction flow and using already existing circuit implementations to hide the transient error.
Claims16
1-15. (cancel)
An apparatus, comprising:
- at least two processors, each processor including a plurality of pipeline stages for processing at least some of the same instructions;
- wherein each pipeline stage includes a parity bit generator to generate at least one parity bit for each pipeline stage;
- and
- a comparing circuit to compare the parity bit of a stage of one of the at least two processors to the parity bit of the same stage of another of the at least two processors, and indicate an error when the parity bits are different in value.
1 more element
A machine-readable medium having stored thereon a plurality of executable instructions, the plurality of instructions comprising instructions to:
- process at least some of the same instructions for at least two processors;
- compare at least one parity bit of a first pipeline stage for one processor with at least one parity bit of a second pipeline stage of another processor performing a similar function as the pipeline stage;
- and
- indicate an error when the parity bits are different in value.
1 more element
A system comprising:
- a memory storing a plurality of instructions;
- at least two processors, each processor coupled to said memory and including a plurality of pipeline stages for processing at least some of the same instructions from said memory;
- wherein each pipeline stage includes a parity bit generator to generate at least one parity bit for each pipeline stage;
- and
- a comparing circuit to compare the parity bit of a stage of one of the at least two processors to the parity bit of the same stage of another of the at least two processors, and indicate an error when the parity bits are different in value.
2 more elements
Dependencies are inferred from the claim text.