Computer system and memory control method thereof
AssigneeWistron Corporation
InventorsChun-Yi Lai, Fu-Yuan Tai, Pao-Chi Sun, Kuo-Jung Peng, Fan-Chen Chang, Hong-Chi Lin, Yuan-Hao Chang
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Abstract
A computer system unaffected by memory module instability. The computer system writes data to a plurality of memory modules. If non-recoverable errors occur in one memory module or the number of errors in one memory module reaches a preset value, the computer system reads data from another memory module. Also, a method of controlling the memory modules is disclosed.
Claims20
A computer system, unaffected by memory module instability, comprising:
- at least one memory mirror unit controlling a plurality of memory modules and receiving an error control signal, wherein each of the memory mirror units writes data to the corresponding memory modules during a write cycle and activates a first memory module among the memory modules, reading data during a read cycle;
- a memory controller enabling the error control signal upon detection of a read error in the first memory module, wherein the memory mirror unit disables the first memory module and activates a second memory module among the memory modules when the read error occurs in the first memory module.
A method for controlling memory of a computer system, the method comprising the steps of:
- providing at least one memory mirror unit, each controlling a memory module group having a plurality of memory modules;
- equalizing addresses of the memory modules inside each memory module group;
- writing data to the corresponding memory modules according to a write address during a write cycle;
- and
- reading a first memory module according to a read address during a read cycle;
- wherein the computer system activates an error control signal received by the corresponding memory mirror unit to select a second memory module from corresponding memory modules when a read error occurs in the first memory module.
A method for controlling memory of a computer system, the method comprising the steps of:
- providing at least one the memory mirror unit each controlling a first and second memory module;
- equalizing addresses of the first and second memory modules;
- writing data to first and second memory modules according to a write address during a write cycle;
- and
- reading the corresponding first memory module according to a read address reading data during a read cycle;
- wherein the computer system activates an error control signal received by the corresponding memory mirror unit to select a corresponding second memory module when a read error in the corresponding first memory module is detected.
Dependencies are inferred from the claim text.