US 2004/0205352 A1 · Scrambler circuit

Abstract

This invention is intended to provide a scrambler circuit capable of realizing a data processing device or an IC card having high security enough to prevent information in a memory or information on a bus from being decrypted. The scrambler circuit has to-be-processed data divided into two data blocks and processed data divided into two data blocks, and includes a first scrambler unit that conducts first scrambling to the data block and that outputs first intermediate data, a first arithmetic unit that performs an exclusive OR operation between the data block and the first intermediate data and that outputs the data block, a second scrambler unit that conducts second scrambling to the data block and that outputs second intermediate data, and a second arithmetic unit that performs an exclusive OR operation between the second intermediate data and the data block and that outputs the data block.

Claims37

Dependent claims

A scrambler circuit for converting a to-be-processed data having at least four bits into a processed data having as many bits as the to-be-processed data by a predetermined scrambling, wherein

said to-be-processed data is divided into a first data block having at least two bits and a second data block having as many bits as said first data block, and said processed data is divided into a third data block and a fourth data block each having as many bits as said first data block, and wherein
said scrambler circuit comprises:
a first scrambler unit that performs a predetermined first scrambling to said first data block, and that outputs a first intermediate data having as many bits as said first data block
a first arithmetic unit that performs an exclusive OR operation between said second data block and said first intermediate data for each bit, and that outputs said third data block
a second scrambler unit that performs one of said first scrambling and a second scrambling different from the first scrambling to said third data block, and that outputs a second intermediate data having as many bits as said third data block and
a second arithmetic unit that performs an exclusive OR operation between said second intermediate data and said first data block for each bit, and that outputs said fourth data block.

3 more elements

A descrambler circuit for inversely converting a scrambled data having at least four bits into an unprocessed data having as many bits as the scrambled data by a predetermined descrambling, wherein

said scrambled data is divided into a fifth data block having at least two bits and a sixth data block having as many bits as said fifth data block,
and said unprocessed data is divided into a seventh data block and an eighth data block each having as many bits as said fifth data block, and
wherein said descrambler circuit comprises:
a third scrambler unit that performs a predetermined third scrambling to said fifth data block, and that outputs a third intermediate data having as many bits as said fifth data block;
a third arithmetic unit that performs an exclusive OR operation between said sixth data block and said third intermediate data for each bit, and that outputs said seventh data block;
a fourth scrambler unit that performs one of said third scrambling and a fourth scrambling different from the third scrambling to said seventh data block, and that outputs a fourth intermediate data having as many bits as said seventh data block;
and
a fourth arithmetic unit that performs an exclusive OR operation between said fourth intermediate data and said fifth data block for each bit, and that outputs said eighth data block.

5 more elements

Dependencies are inferred from the claim text.

Scrambler circuit

Life of this patent

Scrambler circuit

Life of this patent

Abstract

Claims37