Integrated memory having redundant units of memory cells and method for testing an integrated memory

A method for testing an integrated memory, the integrated memory having a plurality of memory cells in a memory cell array, the memory cells being combined to form individually addressable normal units, a plurality of redundant units of memory cells for respectively replacing one of the normal units on an address basis, a memory unit for storing, in a normal mode, an address for one of the normal units which needs to be replaced by one of the redundant units, a comparison unit which is connected to an address bus in the memory and to an output of the memory unit for comparing an address which is present on the address bus with an address stored in the memory unit and for activating one of the redundant units in the event of a match being identified, the method comprising:

• activating a test mode;
• resetting the memory unit to an initial state;
• storing an address for one of the redundant units in the memory unit;
• writing an identification code to the one of the redundant units;
• deactivating the test mode;
• setting the memory unit using the address for one of the normal units which needs to be replaced;
• accessing the memory cell array;
• applying addresses for normal units to the address bus for reading the memory cell array;
• reading the memory cell array;
• and
• associating the identification code which is read with the address for the normal unit addressed for this reading operation.