Method and apparatus for detecting memory device interface

A computer system comprising:

• a CPU;
• a memory system;
• support logic coupled to both the CPU and the memory system;
• a multiplexed bus interface coupled to the support logic and controllable by the CPU executing instructions;
• a multiplexed bus coupled to and controlled by the multiplexed bus interface;
• wherein the multiplexed bus is comprised of a plurality of common signal lines to transfer addresses, commands and data with protocols and timings to support activity with either one of a device having a first bus type interface and a device having a second bus type interface;
• and
• a first device coupled to the multiplexed bus, wherein the first device is a non-volatile memory device having a first bus type interface and storing a plurality of instructions to be executed by the CPU.

A method comprising:

• driving a first coordinating signal line of a multiplexed bus active to signal a device having a first bus type interface that might be coupled to the multiplexed bus;
• attempting to carry out a first form of activity on the multiplexed bus using protocols and timings appropriate to support a transfer of addresses, commands and data across a plurality of common signal lines of the multiplexed bus with a device having a first bus type interface;
• driving the first coordinating signal line of the multiplexed bus inactive if no device responds to the first form of activity;
• driving a second coordinating signal line of the multiplexed bus active to signal a device having a second bus type interface that might be coupled to the multiplexed bus if no device responds to the first form of activity;
• and
• attempting to carry out a second form of activity on the multiplexed bus using protocols and timings appropriate to support a transfer of addresses, commands and data across the plurality of common signal lines of the multiplexed bus with a device having a second bus type interface if no device responds to the first form of activity.

A machine-accessible medium comprising code that when executed by a processor within an electronic device, causes the electronic device to:

• drive a first coordinating signal line of a multiplexed bus active to signal a device having a first bus type interface that might be coupled to the multiplexed bus;
• attempt to carry out a first form of activity on the multiplexed bus using protocols and timings appropriate to support a transfer of addresses, commands and data across a plurality of common signal lines of the multiplexed bus with a device having a first bus type interface;
• drive the first coordinating signal line of the multiplexed bus inactive if no device responds to the first form of activity;
• drive a second coordinating signal line of the multiplexed bus active to signal a device having a second bus type interface that might be coupled to the multiplexed bus if no device responds to the first form of activity;
• and
• attempt to carry out a second form of activity on the multiplexed bus using protocols and timings appropriate to support a transfer of addresses, commands and data across the plurality of common signal lines of the multiplexed bus with a device having a second bus type interface if no device responds to the first form of activity.