Can microcontroller that permits concurrent access to different segments of a common memory by both the processor core and the DMA engine thereof

A microcontroller that supports a plurality of message objects, comprising:

• a processor core that runs applications;
• a module that processes incoming messages;
• data memory including a first memory segment that provides a plurality of message buffers associated with respective ones of the message objects, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects, the memory-mapped registers for each message object containing respective command/control fields for configuration and setup of that message object;
• and,
• a memory interface unit that permits the processor core and the module to concurrently access a different respective one of the first and second memory segments, and that arbitrates access to the same one of the first and second memory segments when the processor core and the module request concurrent access to the same one of the first and second memory segments.

A microcontroller that supports a plurality of message objects, comprising:

• a processor core that runs applications;
• a module that processes incoming messages, wherein the processor core and the module are contained on a single integrated circuit chip;
• data memory including a first memory space that is located on the integrated circuit chip and a second memory space that is located off the integrated circuit chip, the first memory space including a first memory segment that provides at least a portion of a message buffer memory space that includes a plurality of message buffers associated with respective ones of the message objects, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects, the memory-mapped registers for each message object containing respective command/control fields for configuration and setup of that message object;
• and,
• a memory interface unit that permits the processor core and the module to concurrently access a different respective one of the first and second memory spaces, that permits the processor core and the module to concurrently access a different respective one of the first and second memory segments, and that arbitrates access to the second memory space and that arbitrates access to the same one of the first and second memory segments when the processor core and the module request concurrent access to the second memory space or to the same one of the first and second memory segments.

A method for operating a microcontroller that supports a plurality of message objects, the microcontroller including a processor core that runs applications, a module that processes incoming messages, and a data memory including a first memory space that is located on an integrated circuit chip on which the microcontroller and the module are incorporated, and a second memory space that is located off the integrated circuit chip, the first memory space including a first memory segment that provides at least a portion of a message buffer memory space that includes a plurality of message buffers associated with respective ones of the message objects, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects, the memory-mapped registers for each message object containing respective command/control fields for configuration and setup of that message object, the method comprising:

• permitting the processor core and the module to concurrently access a different respective one of the first and second memory spaces;
• permitting the processor core and the module to concurrently access a different respective one of the first and second memory segments;
• arbitrating access to the second memory space when the processor core and the module request concurrent access to the second memory space;
• and,
• arbitrating access to the same one of the first and second memory segments when the processor core and the CAN/CAL module request concurrent access to the first and second memory segments.

A bus station comprising a microcontroller that supports a plurality of message objects, comprising:

• a processor core that runs applications;
• a module that processes incoming messages;
• data memory including a first memory segment that provides a plurality of message buffers associated with respective ones of the message objects, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects, the memory-mapped registers for each message object containing respective command/control fields for configuration and setup of that message object;
• and,
• a memory interface unit that permits the processor core and the module to concurrently access a different respective one of the first and second memory segments, and that arbitrates access to the same one of the first and second memory segments when the processor core and the module request concurrent access to the same one of the first and second memory segments.

A bus system comprising a microcontroller that supports a plurality of message objects, comprising:

• a processor core that runs applications;
• a module that processes incoming messages;
• data memory including a first memory segment that provides a plurality of message buffers associated with respective ones of the message objects, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects, the memory-mapped registers for each message object containing respective command/control fields for configuration and setup of that message object;
• and,
• a memory interface unit that permits the processor core and the module to concurrently access a different respective one of the first and second memory segments, and that arbitrates access to the same one of the first and second memory segments when the processor core and the module request concurrent access to the same one of the first and second memory segments.