Digital signal processor with a byte DMA controller
AssigneeFaraday Technology Corp.
InventorKuei-yi Chou
Life of this patent
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Abstract
A digital signal processor includes a byte direct memory access (DMA) controller and an external memory controller, both of which are coupled to each other. The external memory controller is coupled to a byte memory and other external memories through a common data bus. The byte DMA controller performs a byte DMA operation to the byte memory through the common data bus by controlling the external memory, thereby avoiding an additional data bus. As a result, the digital signal processor according to the present invention has less connecting terminals and achieves a size reduction.
Claims11
A digital signal processor coupled wit a byte memory and an external memory through a common data bus, comprising:
- an internal memory stored with at least one word, each of which consists of a plurality of bytes;
- an external memory controller coupled with the common data bus;
- a byte direct memory access DMA) controller coupled with the external memory controller, including:
- a byte DMA steal request circuit for outputting a write steal request;
- a data buffer coupled with the internal memory for receiving in format of a word the at least one word stored in the internal memory during an execution of the write steal request;
- a byte DMA request circuit for outputting a write request into the external memory controller after the data buffer has received the at least one word stored in the internal memory;
- and
- a byte DMA waiting circuit for periodically outputting a waiting end signal into the external memory controller at the end of a programmed period;
- and
- a steal request priority scheduler for receiving the write steal request and making a schedule for the execution of the write steal request, wherein:
- the external memory controller makes a schedule for an execution of the write request, and
- during the execution of the write request, the external memory controller in response to the waiting end signal transfers in format of a byte the at least one word from the data buffer through the common data bus into the byte memory.
A digital signal processor coupled with a byte memory and an external memory through a common data bus, in which at least one word is stored in the byte memory and each of the at least one word consists of a plurality of bytes, the digital signal processor comprising:
- an external memory controller coupled with the common data bus;
- a byte direct memory access (DMA) controller coupled with the external memory controller, including:
- a byte DMA request circuit for outputting a read request into the external memory controller;
- a byte DMA waiting circuit for periodically outputting a waiting end signal into the external memory controller at the end of a programmed period;
- a data buffer for receiving the at least one word stored in the byte memory during an execution of the read request;
- and
- a byte DMA steal request circuit for outputting a read steal request after the data buffer has received the at least one word stored in the byte memory,
- a steal request priority scheduler for receiving the read steal request, making a schedule for an execution of the read steal request, and outputting a steal acknowledgement into the external memory controller during the execution of the read steal request;
- and
- an internal memory coupled with the data buffer for receiving in format of a word the at least one word stored in the data buffer during the execution of the read steal request, wherein:
- the external memory controller makes a schedule for the execution of the read request, and
- during the execution of the read request, the external memory controller in response to the waiting end signal transfers in format of a byte the at least one word from the byte memory through the common data bus into the data buffer.
Dependencies are inferred from the claim text.