Semiconductor memory device having a test mode for testing an operation state
AssigneeRenesas Technology Corp.
InventorsShuichi Horihata, Kenji Tokami
Life of this patent
Estimating the term…
Abstract
A bit line equalize circuit equalizes one and the other of bit lines to one and the other of predetermined bit line potentials in response to activation of a bit line equalize signal, respectively. The one predetermined bit line potential on the one bit lines is higher than the other predetermined bit line potential on the other bit line. Thereby, a read error reflecting WL-BC(BL) shorting and WL-SC(SN) shorting can be detected further rapidly without increasing a circuit area.
Claims11
A semiconductor memory device of a single-memory-cell structure having a test mode for testing an operation state, comprising:
- a plurality of word lines arranged in a row direction;
- a bit line pair arranged in a column direction;
- a plurality of memory cells configured such that only one of the memory cells on each of said plurality of word lines is arranged for the bit line pair, and corresponds to one bit line alternately in said pair;
- a bit line equalize circuit equalizing potentials on said bit line pair;
- and
- a bit line isolation control circuit performing electrical connection and isolation of said paired bit lines, wherein
- said bit line equalize circuit or said bit line isolation control circuit can control the potential on each of the paired bit lines independently of the other in the test mode.
A semiconductor memory device of a twin-memory-cell structure having a test mode for testing an operation state, comprising:
- a plurality of word lines arranged in a row direction;
- a bit line pair arranged in a column direction;
- a plurality of memory cells configured such that two of the memory cells arranged on each of said plurality of word lines correspond to the paired bit lines, respectively;
- a bit line equalize circuit equalizing potentials on said bit line pair;
- and
- a bit line isolation control circuit performing electrical connection and isolation of said paired bit lines, wherein
- said bit line equalize circuit or said bit line isolation control circuit can control the potential on each of the paired bit lines independently of the other in the test mode.
A semiconductor memory device having a test mode for testing an operation state, comprising:
- a plurality of word lines arranged in a row direction;
- a bit line pair arranged in a column direction;
- a first memory cell group connected to one of said paired bit lines supplied with a first cell plate potential;
- and
- a second memory cell group connected to the other of said paired bit lines supplied with a second cell plate potential.
Dependencies are inferred from the claim text.