Methods for forming polycrystalline silicon layer and fabricating polycrystalline silicon thin film transistor

A method of forming a polycrystalline silicon layer on an amorphous silicon layer on a substrate, comprising:

• depositing a catalyst metal on the amorphous silicon layer;
• disposing first, second, third and fourth electrodes contacting the amorphous silicon layer such that the first and second electrodes are disposed along a first direction and the third and fourth electrodes are disposed along a second direction, the second direction being different from the first direction;
• and
• heating the amorphous silicon layer under a temperature and simultaneously applying a first voltage to the first and second electrodes and a second voltage to the third and fourth electrodes.

A method of forming a polycrystalline silicon thin film transistor, comprising:

• forming an amorphous silicon layer on a substrate;
• depositing a catalyst metal on the amorphous silicon layer;
• disposing first and second electrodes contacting the amorphous silicon layer along a first direction;
• heating the amorphous silicon layer under a first temperature and simultaneously applying a first voltage to the first and second electrodes to form a first crystallized amorphous silicon layer;
• disposing third and fourth electrodes contacting the first crystallized amorphous silicon layer along a second direction, the second direction being different from the first direction;
• heating the first crystallized amorphous silicon layer under a second temperature and simultaneously applying a second voltage to the third and fourth electrodes to form a polycrystalline silicon layer;
• patterning the polycrystalline silicon layer to form an active layer;
• forming a gate insulating layer on the active layer;
• forming a gate electrode on the gate insulating layer;
• doping the active layer with impurities to form source and drain regions in the active layer;
• forming an interlayer insulating layer on the gate electrode, the interlayer insulating layer having source contact hole exposing the source region and drain contact hole exposing the drain region;
• and
• forming source and drain electrodes on the interlayer insulating layer, the source electrode being connected to the source region through the source contact hole, the drain electrode being connected to the drain region through the drain contact hole.

A method of forming a polycrystalline silicon thin film transistor, comprising:

• forming an amorphous silicon layer on a substrate;
• depositing a catalyst metal on the amorphous silicon layer;
• disposing first, second, third and fourth electrodes contacting the amorphous silicon layer such that the first and second electrodes are disposed along a first direction and the third and fourth electrodes are disposed along a second direction, the second direction being different from the first direction;
• heating the amorphous silicon layer under a temperature and simultaneously applying a first voltage to the first and second electrodes and a second voltage to the third and fourth electrodes to form a polycrystalline silicon layer;
• patterning the polycrystalline silicon layer to form an active layer;
• forming a gate insulating layer on the active layer;
• forming a gate electrode on the gate insulating layer;
• doping the active layer with impurities to form source and drain regions in the active layer;
• forming an interlayer insulating layer on the gate electrode, the interlayer insulating layer having source contact hole exposing the source region and drain contact hole exposing the drain region;
• and
• forming source and drain electrodes on the interlayer insulating layer, the source electrode being connected to the source region through the source contact hole, the drain electrode being connected to the drain region through the drain contact hole.