Semiconductor memory system and method for multi-sector erase operation
AssigneeSamsung Electronics Co., Ltd.
InventorsDong-Hyuk Chae, Heung-Soo Lim
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Abstract
The disclosure is a semiconductor memory device operable with a multi-sector erase mode for a multiplicity of memory chips, including a cell array, a register circuit containing information for a sector to be erased, an address clock driving circuit for contemporaneously generating an address clock signal from each memory chips, a counter for generating address signals in sequence, a core driver for executing an erase operation for the sector, and a control circuit thereof.
Claims21
A memory system having a plurality of memory chips, comprising:
- an address clock driver to generate an address clock signal in response to a current chip signal and an address count-up signal;
- a counter togenerate an address including a chip information and a sector information;
- and
- a control circuit to generate the address count-up signal with reference to that the sector information corresponds to a sector to be erased.
A memory system having a plurality of memory chips, comprising:
- a memory cell array constructed of a plurality of sectors;
- a register circuit tostore a loaded sector information about a sector to be erased;
- an address clock driver to generate address clock signals contemporaneously for the chips in response to a current chip signal and an address count-up signal;
- a counter to generate an address including a chip information and a sector information;
- a control circuit to generate the address count-up signal and an erase enable signal with reference to that the loaded sector information corresponds to the sector information of the counter;
- and
- a core driver to carry out an erase operation for a corresponding sector in response to the erase enable signal.
A memory system having a plurality of memory chips, comprising:
- a first bus totransfer control signals;
- a second bus to transfer address and data signals;
- and
- a plurality of memory chips connected to the first and second buses;
- wherein each memory chip comprises:
- a memory cell array constructed of a plurality of sectors;
- a register circuit to store a loaded sector information about a sector to be erased;
- an address clock driver to generate address clock signals contemporaneously for the chips in response to a current chip signal and an address count-up signal;
- a counter to generate an address including a chip information and a sector information;
- a control circuit to generate the address count-up signal and an erase enable signal with reference to that the loaded sector information corresponds to the sector information of the counter;
- and
- a core driver to carry out an erase operation for a corresponding sector in response to the erase enable signal.
A method of erasing multi-sectors in a multi-chip package including a counter, a control circuit, and a register circuit, the method comprising:
- initializing an address of the counter;
- determining whether a chip information of the counter is identical to a chip selection information of the control circuit;
- determining whether a sector information of the counter is identical to a loaded sector information of the register circuit when the chip information of the counter is identical to the chip selection information of the control circuit;
- erasing a sector corresponding to the loaded sector information when the sector information of the counter is identical to the loaded sector information;
- and
- terminating the multi-sector erase operation when an erased sector is the last sector.
Dependencies are inferred from the claim text.