Virtual dual-port synchronous RAM architecture
AssigneeQUALCOMM Incorporated
InventorTao Li
Life of this patent
Estimating the term…
Abstract
Disclosed is a virtual dual-port synchronous RAM device, system, and method, wherein the design requires minimal hardware cost compared with a dual-port RAM architecture or the traditional architecture used with a single-port RAM. Disclosed is a read/write memory device including means to accept signals from a first host and a second host, the first host having a first clock and the second host having a second clock, the signals including a first clock signal and a second clock, a clock switching means for switching between the first clock signal and the second clock signal, a single-port random access memory (RAM) module for storing data, and a RAM clock for synchronizing the clock signals with the RAM module.
Claims21
A read/write memory device, comprising:
- a clock switching means for switching between a first clock signal and a second clock signal;
- a single-port random access memory (RAM) module for storing data;
- and
- a random access memory (RAM) clock for synchronizing the clock signals with the random access memory (RAM) module.
A read/write memory system, comprising:
- a first host and a second host, the first host having a first clock generating a first clock signal and the second host having a second clock generating a second clock signal;
- a clock switch for switching between the first clock signal and the second clock signal;
- a single-port random access memory (RAM) module for storing data;
- and
- a RAM clock for synchronizing the clock signals with the random access memory (RAM) module.
A method for storing and recalling data in a memory device, comprising the steps of:
- generating a first clock signal and a second clock signal;
- switching between the first clock signal and the second clock signal;
- allowing either the first clock signal or the second clock signal access to a single-port random access memory (RAM) module;
- and
- storing and recalling the stored data from the random access memory (RAM) module.
A method for storing and recalling data in a memory device, comprising the steps of:
- switching between a first clock signal and a second clock signal;
- storing data in a single port random access memory (RAM) module;
- and
- synchronizing the clock signals with the random access memory (RAM) module.
Dependencies are inferred from the claim text.