Programmable delay for self-timed-margin

A method for controlling the timing of an output signal on a signal path in relation to an input signal on the signal path, comprising:

• generating a plurality of delayed versions of the input signal;
• programmably determining a desired timing margin in a signal path of said system;
• and
• selecting one of the plurality of delayed versions of the input signal that corresponds to the desired timing margin and outputting the selected delayed version of the input signal as the output signal.

A control system for programmably adjusting the clock delay in a self-timed memory system for accessing data in a memory system in response to the assertion of a clock signal, the memory system including a memory array of memory cells which are addressed by a first address signal and a corresponding array of sense amplifiers receiving a sense enable signal for enabling the sense amplifiers to sense data in the addressed memory cells, said control system comprising:

• address decode circuitry to generate a first address signal in response to a clock signal;
• a sense enable signal generator to generate a plurality of sense enable signals which are delayed with respect to the clock signal and to select one of the plurality of sense enable signals for output as an output sense enable signal to a sense amplifier in response to a control signal;
• and
• a control circuit for generating the control signal to specify a desired amount of delay between the output sense enable signal and the first address signal.